Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 5 | * Copyright 2013 Google Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 18 | #include <delay.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | #include <types.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | #include <arch/io.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <cpu/x86/cache.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <cpu/x86/smm.h> |
| 25 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 26 | #include <halt.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | #include <pc80/mc146818rtc.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame^] | 28 | #include <southbridge/intel/common/finalize.h> |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 29 | #include <northbridge/intel/haswell/haswell.h> |
| 30 | #include <cpu/intel/haswell/haswell.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame^] | 31 | #include "me.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | #include "pch.h" |
| 33 | |
| 34 | #include "nvs.h" |
| 35 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | |
| 37 | static u8 smm_initialized = 0; |
| 38 | |
| 39 | /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located |
| 40 | * by coreboot. |
| 41 | */ |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 42 | static global_nvs_t *gnvs; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | global_nvs_t *smm_get_gnvs(void) |
| 44 | { |
| 45 | return gnvs; |
| 46 | } |
| 47 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 48 | int southbridge_io_trap_handler(int smif) |
| 49 | { |
| 50 | switch (smif) { |
| 51 | case 0x32: |
| 52 | printk(BIOS_DEBUG, "OS Init\n"); |
| 53 | /* gnvs->smif: |
| 54 | * On success, the IO Trap Handler returns 0 |
| 55 | * On failure, the IO Trap Handler returns a value != 0 |
| 56 | */ |
| 57 | gnvs->smif = 0; |
| 58 | return 1; /* IO trap handled */ |
| 59 | } |
| 60 | |
| 61 | /* Not handled */ |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | /** |
| 66 | * @brief Set the EOS bit |
| 67 | */ |
| 68 | void southbridge_smi_set_eos(void) |
| 69 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 70 | enable_smi(EOS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static void busmaster_disable_on_bus(int bus) |
| 74 | { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 75 | int slot, func; |
| 76 | unsigned int val; |
| 77 | unsigned char hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 78 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 79 | for (slot = 0; slot < 0x20; slot++) { |
| 80 | for (func = 0; func < 8; func++) { |
| 81 | u32 reg32; |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 82 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 83 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 84 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 85 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 86 | if (val == 0xffffffff || val == 0x00000000 || |
| 87 | val == 0x0000ffff || val == 0xffff0000) |
| 88 | continue; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 89 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 90 | /* Disable Bus Mastering for this one device */ |
| 91 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 92 | reg32 &= ~PCI_COMMAND_MASTER; |
| 93 | pci_write_config32(dev, PCI_COMMAND, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 95 | /* If this is a bridge, then follow it. */ |
| 96 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 97 | hdr &= 0x7f; |
| 98 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
| 99 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
| 100 | unsigned int buses; |
| 101 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 102 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 103 | } |
| 104 | } |
| 105 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 106 | } |
| 107 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 108 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 109 | static void southbridge_smi_sleep(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | { |
| 111 | u8 reg8; |
| 112 | u32 reg32; |
| 113 | u8 slp_typ; |
| 114 | u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 115 | u16 pmbase = get_pmbase(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | |
| 117 | // save and recover RTC port values |
| 118 | u8 tmp70, tmp72; |
| 119 | tmp70 = inb(0x70); |
| 120 | tmp72 = inb(0x72); |
| 121 | get_option(&s5pwr, "power_on_after_fail"); |
| 122 | outb(tmp70, 0x70); |
| 123 | outb(tmp72, 0x72); |
| 124 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | /* First, disable further SMIs */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 126 | disable_smi(SLP_SMI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 127 | |
| 128 | /* Figure out SLP_TYP */ |
| 129 | reg32 = inl(pmbase + PM1_CNT); |
| 130 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 131 | slp_typ = acpi_sleep_from_pm1(reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | |
| 133 | /* Do any mainboard sleep handling */ |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 134 | mainboard_smi_sleep(slp_typ); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 136 | /* USB sleep preparations */ |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 137 | #if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 138 | usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); |
| 139 | usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 140 | #endif |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 141 | usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 142 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 143 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | /* Log S3, S4, and S5 entry */ |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 145 | if (slp_typ >= ACPI_S3) |
| 146 | elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 147 | #endif |
| 148 | |
| 149 | /* Next, do the deed. |
| 150 | */ |
| 151 | |
| 152 | switch (slp_typ) { |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 153 | case ACPI_S0: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 154 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 155 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 156 | case ACPI_S1: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 157 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 158 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 159 | case ACPI_S3: |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 160 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 161 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 162 | /* Invalidate the cache before going to S3 */ |
| 163 | wbinvd(); |
| 164 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 165 | case ACPI_S4: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 166 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 167 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 168 | case ACPI_S5: |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 169 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 170 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 171 | /* Disable all GPE */ |
| 172 | disable_all_gpe(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 173 | |
| 174 | /* Always set the flag in case CMOS was changed on runtime. For |
| 175 | * "KEEP", switch to "OFF" - KEEP is software emulated |
| 176 | */ |
Aaron Durbin | 89f79a0 | 2012-10-31 23:05:25 -0500 | [diff] [blame] | 177 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 178 | if (s5pwr == MAINBOARD_POWER_ON) { |
| 179 | reg8 &= ~1; |
| 180 | } else { |
| 181 | reg8 |= 1; |
| 182 | } |
Aaron Durbin | 89f79a0 | 2012-10-31 23:05:25 -0500 | [diff] [blame] | 183 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 184 | |
| 185 | /* also iterates over all bridges on bus 0 */ |
| 186 | busmaster_disable_on_bus(0); |
| 187 | break; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 188 | default: |
| 189 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 190 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | /* Write back to the SLP register to cause the originally intended |
| 194 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 195 | * sleep happen. |
| 196 | */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 197 | enable_pm1_control(SLP_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 198 | |
| 199 | /* Make sure to stop executing code here for S3/S4/S5 */ |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 200 | if (slp_typ >= ACPI_S3) |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 201 | halt(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 202 | |
| 203 | /* In most sleep states, the code flow of this function ends at |
| 204 | * the line above. However, if we entered sleep state S1 and wake |
| 205 | * up again, we will continue to execute code in this function. |
| 206 | */ |
| 207 | reg32 = inl(pmbase + PM1_CNT); |
| 208 | if (reg32 & SCI_EN) { |
| 209 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 210 | disable_pm1_control(SLP_EN | SLP_TYP); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 211 | } |
| 212 | } |
| 213 | |
| 214 | /* |
| 215 | * Look for Synchronous IO SMI and use save state from that |
| 216 | * core in case we are not running on the same core that |
| 217 | * initiated the IO transaction. |
| 218 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 219 | static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) |
| 220 | { |
| 221 | em64t101_smm_state_save_area_t *state; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 222 | int node; |
| 223 | |
| 224 | /* Check all nodes looking for the one that issued the IO */ |
| 225 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 226 | state = smm_get_save_state(node); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 227 | |
Elyes HAOUAS | 581fe58 | 2018-04-26 09:57:07 +0200 | [diff] [blame] | 228 | /* Check for Synchronous IO (bit0 == 1) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 229 | if (!(state->io_misc_info & (1 << 0))) |
| 230 | continue; |
| 231 | |
Elyes HAOUAS | 581fe58 | 2018-04-26 09:57:07 +0200 | [diff] [blame] | 232 | /* Make sure it was a write (bit4 == 0) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 233 | if (state->io_misc_info & (1 << 4)) |
| 234 | continue; |
| 235 | |
| 236 | /* Check for APMC IO port */ |
| 237 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 238 | continue; |
| 239 | |
| 240 | /* Check AX against the requested command */ |
| 241 | if ((state->rax & 0xff) != cmd) |
| 242 | continue; |
| 243 | |
| 244 | return state; |
| 245 | } |
| 246 | |
| 247 | return NULL; |
| 248 | } |
| 249 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 250 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 251 | static void southbridge_smi_gsmi(void) |
| 252 | { |
| 253 | u32 *ret, *param; |
| 254 | u8 sub_command; |
| 255 | em64t101_smm_state_save_area_t *io_smi = |
| 256 | smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); |
| 257 | |
| 258 | if (!io_smi) |
| 259 | return; |
| 260 | |
| 261 | /* Command and return value in EAX */ |
| 262 | ret = (u32*)&io_smi->rax; |
| 263 | sub_command = (u8)(*ret >> 8); |
| 264 | |
| 265 | /* Parameter buffer in EBX */ |
| 266 | param = (u32*)&io_smi->rbx; |
| 267 | |
| 268 | /* drivers/elog/gsmi.c */ |
| 269 | *ret = gsmi_exec(sub_command, param); |
| 270 | } |
| 271 | #endif |
| 272 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 273 | static void southbridge_smi_apmc(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 274 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 275 | u8 reg8; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 276 | em64t101_smm_state_save_area_t *state; |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 277 | static int chipset_finalized = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 278 | |
| 279 | /* Emulate B2 register as the FADT / Linux expects it */ |
| 280 | |
| 281 | reg8 = inb(APM_CNT); |
| 282 | switch (reg8) { |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 283 | case APM_CNT_FINALIZE: |
| 284 | if (chipset_finalized) { |
| 285 | printk(BIOS_DEBUG, "SMI#: Already finalized\n"); |
| 286 | return; |
| 287 | } |
| 288 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame^] | 289 | intel_me_finalize_smm(); |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 290 | intel_pch_finalize_smm(); |
| 291 | intel_northbridge_haswell_finalize_smm(); |
| 292 | intel_cpu_haswell_finalize_smm(); |
| 293 | |
| 294 | chipset_finalized = 1; |
| 295 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 296 | case APM_CNT_CST_CONTROL: |
| 297 | /* Calling this function seems to cause |
| 298 | * some kind of race condition in Linux |
| 299 | * and causes a kernel oops |
| 300 | */ |
| 301 | printk(BIOS_DEBUG, "C-state control\n"); |
| 302 | break; |
| 303 | case APM_CNT_PST_CONTROL: |
| 304 | /* Calling this function seems to cause |
| 305 | * some kind of race condition in Linux |
| 306 | * and causes a kernel oops |
| 307 | */ |
| 308 | printk(BIOS_DEBUG, "P-state control\n"); |
| 309 | break; |
| 310 | case APM_CNT_ACPI_DISABLE: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 311 | disable_pm1_control(SCI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 312 | printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); |
| 313 | break; |
| 314 | case APM_CNT_ACPI_ENABLE: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 315 | enable_pm1_control(SCI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 316 | printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); |
| 317 | break; |
| 318 | case APM_CNT_GNVS_UPDATE: |
| 319 | if (smm_initialized) { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 320 | printk(BIOS_DEBUG, |
| 321 | "SMI#: SMM structures already initialized!\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 322 | return; |
| 323 | } |
| 324 | state = smi_apmc_find_state_save(reg8); |
| 325 | if (state) { |
| 326 | /* EBX in the state save contains the GNVS pointer */ |
| 327 | gnvs = (global_nvs_t *)((u32)state->rbx); |
| 328 | smm_initialized = 1; |
| 329 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
| 330 | } |
| 331 | break; |
Duncan Laurie | 78145a5 | 2013-08-21 13:16:21 -0700 | [diff] [blame] | 332 | case 0xca: |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 333 | usb_xhci_route_all(); |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 334 | break; |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 335 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 336 | case ELOG_GSMI_APM_CNT: |
| 337 | southbridge_smi_gsmi(); |
| 338 | break; |
| 339 | #endif |
| 340 | } |
| 341 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 342 | mainboard_smi_apmc(reg8); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 343 | } |
| 344 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 345 | static void southbridge_smi_pm1(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 346 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 347 | u16 pm1_sts = clear_pm1_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 348 | |
| 349 | /* While OSPM is not active, poweroff immediately |
| 350 | * on a power button event. |
| 351 | */ |
| 352 | if (pm1_sts & PWRBTN_STS) { |
| 353 | // power button pressed |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 354 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 355 | elog_add_event(ELOG_TYPE_POWER_BUTTON); |
| 356 | #endif |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 357 | disable_pm1_control(-1UL); |
| 358 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 359 | } |
| 360 | } |
| 361 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 362 | static void southbridge_smi_gpe0(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 363 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 364 | clear_gpe_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 365 | } |
| 366 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 367 | static void southbridge_smi_gpi(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 368 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 369 | mainboard_smi_gpi(clear_alt_smi_status()); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 370 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 371 | /* Clear again after mainboard handler */ |
| 372 | clear_alt_smi_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 373 | } |
| 374 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 375 | static void southbridge_smi_mc(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 376 | { |
| 377 | u32 reg32; |
| 378 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 379 | reg32 = inl(get_pmbase() + SMI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 380 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 381 | /* Are microcontroller SMIs enabled? */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 382 | if ((reg32 & MCSMI_EN) == 0) |
| 383 | return; |
| 384 | |
| 385 | printk(BIOS_DEBUG, "Microcontroller SMI.\n"); |
| 386 | } |
| 387 | |
| 388 | |
| 389 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 390 | static void southbridge_smi_tco(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 391 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 392 | u32 tco_sts = clear_tco_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 393 | |
| 394 | /* Any TCO event? */ |
| 395 | if (!tco_sts) |
| 396 | return; |
| 397 | |
| 398 | if (tco_sts & (1 << 8)) { // BIOSWR |
| 399 | u8 bios_cntl; |
| 400 | |
Aaron Durbin | 89f79a0 | 2012-10-31 23:05:25 -0500 | [diff] [blame] | 401 | bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 402 | |
| 403 | if (bios_cntl & 1) { |
| 404 | /* BWE is RW, so the SMI was caused by a |
| 405 | * write to BWE, not by a write to the BIOS |
| 406 | */ |
| 407 | |
| 408 | /* This is the place where we notice someone |
| 409 | * is trying to tinker with the BIOS. We are |
| 410 | * trying to be nice and just ignore it. A more |
| 411 | * resolute answer would be to power down the |
| 412 | * box. |
| 413 | */ |
| 414 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 415 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, |
| 416 | (bios_cntl & ~1)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 417 | } /* No else for now? */ |
| 418 | } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ |
| 419 | /* Handle TCO timeout */ |
| 420 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 421 | } |
| 422 | } |
| 423 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 424 | static void southbridge_smi_periodic(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 425 | { |
| 426 | u32 reg32; |
| 427 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 428 | reg32 = inl(get_pmbase() + SMI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 429 | |
| 430 | /* Are periodic SMIs enabled? */ |
| 431 | if ((reg32 & PERIODIC_EN) == 0) |
| 432 | return; |
| 433 | |
| 434 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 435 | } |
| 436 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 437 | static void southbridge_smi_monitor(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 438 | { |
| 439 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 440 | u32 trap_sts, trap_cycle; |
| 441 | u32 data, mask = 0; |
| 442 | int i; |
| 443 | |
| 444 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 445 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 446 | |
| 447 | trap_cycle = RCBA32(0x1e10); |
| 448 | for (i=16; i<20; i++) { |
| 449 | if (trap_cycle & (1 << i)) |
| 450 | mask |= (0xff << ((i - 16) << 2)); |
| 451 | } |
| 452 | |
| 453 | |
| 454 | /* IOTRAP(3) SMI function call */ |
| 455 | if (IOTRAP(3)) { |
| 456 | if (gnvs && gnvs->smif) |
| 457 | io_trap_handler(gnvs->smif); // call function smif |
| 458 | return; |
| 459 | } |
| 460 | |
| 461 | /* IOTRAP(2) currently unused |
| 462 | * IOTRAP(1) currently unused */ |
| 463 | |
| 464 | /* IOTRAP(0) SMIC */ |
| 465 | if (IOTRAP(0)) { |
| 466 | if (!(trap_cycle & (1 << 24))) { // It's a write |
| 467 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 468 | data = RCBA32(0x1e18); |
| 469 | data &= mask; |
| 470 | // if (smi1) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 471 | // southbridge_smi_command(data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 472 | // return; |
| 473 | } |
| 474 | // Fall through to debug |
| 475 | } |
| 476 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 477 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", |
| 478 | trap_cycle & 0xfffc); |
| 479 | for (i=0; i < 4; i++) |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 480 | if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 481 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 482 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 483 | printk(BIOS_DEBUG, " read/write: %s\n", |
| 484 | (trap_cycle & (1 << 24)) ? "read" : "write"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 485 | |
| 486 | if (!(trap_cycle & (1 << 24))) { |
| 487 | /* Write Cycle */ |
| 488 | data = RCBA32(0x1e18); |
| 489 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 490 | } |
| 491 | #undef IOTRAP |
| 492 | } |
| 493 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 494 | typedef void (*smi_handler_t)(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 495 | |
| 496 | static smi_handler_t southbridge_smi[32] = { |
| 497 | NULL, // [0] reserved |
| 498 | NULL, // [1] reserved |
| 499 | NULL, // [2] BIOS_STS |
| 500 | NULL, // [3] LEGACY_USB_STS |
| 501 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 502 | southbridge_smi_apmc, // [5] APM_STS |
| 503 | NULL, // [6] SWSMI_TMR_STS |
| 504 | NULL, // [7] reserved |
| 505 | southbridge_smi_pm1, // [8] PM1_STS |
| 506 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 507 | southbridge_smi_gpi, // [10] GPI_STS |
| 508 | southbridge_smi_mc, // [11] MCSMI_STS |
| 509 | NULL, // [12] DEVMON_STS |
| 510 | southbridge_smi_tco, // [13] TCO_STS |
| 511 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 512 | NULL, // [15] SERIRQ_SMI_STS |
| 513 | NULL, // [16] SMBUS_SMI_STS |
| 514 | NULL, // [17] LEGACY_USB2_STS |
| 515 | NULL, // [18] INTEL_USB2_STS |
| 516 | NULL, // [19] reserved |
| 517 | NULL, // [20] PCI_EXP_SMI_STS |
| 518 | southbridge_smi_monitor, // [21] MONITOR_STS |
| 519 | NULL, // [22] reserved |
| 520 | NULL, // [23] reserved |
| 521 | NULL, // [24] reserved |
| 522 | NULL, // [25] EL_SMI_STS |
| 523 | NULL, // [26] SPI_STS |
| 524 | NULL, // [27] reserved |
| 525 | NULL, // [28] reserved |
| 526 | NULL, // [29] reserved |
| 527 | NULL, // [30] reserved |
| 528 | NULL // [31] reserved |
| 529 | }; |
| 530 | |
| 531 | /** |
| 532 | * @brief Interrupt handler for SMI# |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 533 | */ |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 534 | void southbridge_smi_handler(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 535 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 536 | int i; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 537 | u32 smi_sts; |
| 538 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 539 | /* We need to clear the SMI status registers, or we won't see what's |
| 540 | * happening in the following calls. |
| 541 | */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 542 | smi_sts = clear_smi_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 543 | |
| 544 | /* Call SMI sub handler for each of the status bits */ |
| 545 | for (i = 0; i < 31; i++) { |
| 546 | if (smi_sts & (1 << i)) { |
| 547 | if (southbridge_smi[i]) { |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 548 | southbridge_smi[i](); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 549 | } else { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 550 | printk(BIOS_DEBUG, |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 551 | "SMI_STS[%d] occurred, but no " |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 552 | "handler available.\n", i); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 553 | } |
| 554 | } |
| 555 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 556 | } |