Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <types.h> |
| 23 | #include <arch/hlt.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <arch/romcc_io.h> |
| 26 | #include <console/console.h> |
| 27 | #include <cpu/x86/cache.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <cpu/x86/smm.h> |
| 30 | #include <elog.h> |
| 31 | #include <pc80/mc146818rtc.h> |
| 32 | #include "pch.h" |
| 33 | |
| 34 | #include "nvs.h" |
| 35 | |
| 36 | /* We are using PCIe accesses for now |
| 37 | * 1. the chipset can do it |
| 38 | * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind |
| 39 | */ |
| 40 | #include <northbridge/intel/haswell/haswell.h> |
| 41 | #include <northbridge/intel/haswell/pcie_config.c> |
| 42 | |
| 43 | /* While we read PMBASE dynamically in case it changed, let's |
| 44 | * initialize it with a sane value |
| 45 | */ |
| 46 | static u16 pmbase = DEFAULT_PMBASE; |
| 47 | u16 smm_get_pmbase(void) |
| 48 | { |
| 49 | return pmbase; |
| 50 | } |
| 51 | |
| 52 | static u8 smm_initialized = 0; |
| 53 | |
| 54 | /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located |
| 55 | * by coreboot. |
| 56 | */ |
| 57 | static global_nvs_t *gnvs = (global_nvs_t *)0x0; |
| 58 | global_nvs_t *smm_get_gnvs(void) |
| 59 | { |
| 60 | return gnvs; |
| 61 | } |
| 62 | |
| 63 | #if CONFIG_SMM_TSEG |
| 64 | static u32 tseg_base = 0; |
| 65 | u32 smi_get_tseg_base(void) |
| 66 | { |
| 67 | if (!tseg_base) |
| 68 | tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; |
| 69 | return tseg_base; |
| 70 | } |
| 71 | void tseg_relocate(void **ptr) |
| 72 | { |
| 73 | /* Adjust pointer with TSEG base */ |
| 74 | if (*ptr && *ptr < (void*)smi_get_tseg_base()) |
| 75 | *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base()); |
| 76 | } |
| 77 | #endif |
| 78 | |
| 79 | /** |
| 80 | * @brief read and clear PM1_STS |
| 81 | * @return PM1_STS register |
| 82 | */ |
| 83 | static u16 reset_pm1_status(void) |
| 84 | { |
| 85 | u16 reg16; |
| 86 | |
| 87 | reg16 = inw(pmbase + PM1_STS); |
| 88 | /* set status bits are cleared by writing 1 to them */ |
| 89 | outw(reg16, pmbase + PM1_STS); |
| 90 | |
| 91 | return reg16; |
| 92 | } |
| 93 | |
| 94 | static void dump_pm1_status(u16 pm1_sts) |
| 95 | { |
| 96 | printk(BIOS_SPEW, "PM1_STS: "); |
| 97 | if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); |
| 98 | if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); |
| 99 | if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); |
| 100 | if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); |
| 101 | if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); |
| 102 | if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); |
| 103 | if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); |
| 104 | if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); |
| 105 | printk(BIOS_SPEW, "\n"); |
| 106 | int reg16 = inw(pmbase + PM1_EN); |
| 107 | printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); |
| 108 | } |
| 109 | |
| 110 | /** |
| 111 | * @brief read and clear SMI_STS |
| 112 | * @return SMI_STS register |
| 113 | */ |
| 114 | static u32 reset_smi_status(void) |
| 115 | { |
| 116 | u32 reg32; |
| 117 | |
| 118 | reg32 = inl(pmbase + SMI_STS); |
| 119 | /* set status bits are cleared by writing 1 to them */ |
| 120 | outl(reg32, pmbase + SMI_STS); |
| 121 | |
| 122 | return reg32; |
| 123 | } |
| 124 | |
| 125 | static void dump_smi_status(u32 smi_sts) |
| 126 | { |
| 127 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 128 | if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); |
| 129 | if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); |
| 130 | if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); |
| 131 | if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); |
| 132 | if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); |
| 133 | if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); |
| 134 | if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); |
| 135 | if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); |
| 136 | if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); |
| 137 | if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); |
| 138 | if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); |
| 139 | if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); |
| 140 | if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); |
| 141 | if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); |
| 142 | if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); |
| 143 | if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); |
| 144 | if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); |
| 145 | if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); |
| 146 | if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); |
| 147 | printk(BIOS_DEBUG, "\n"); |
| 148 | } |
| 149 | |
| 150 | |
| 151 | /** |
| 152 | * @brief read and clear GPE0_STS |
| 153 | * @return GPE0_STS register |
| 154 | */ |
| 155 | static u32 reset_gpe0_status(void) |
| 156 | { |
| 157 | u32 reg32; |
| 158 | |
| 159 | reg32 = inl(pmbase + GPE0_STS); |
| 160 | /* set status bits are cleared by writing 1 to them */ |
| 161 | outl(reg32, pmbase + GPE0_STS); |
| 162 | |
| 163 | return reg32; |
| 164 | } |
| 165 | |
| 166 | static void dump_gpe0_status(u32 gpe0_sts) |
| 167 | { |
| 168 | int i; |
| 169 | printk(BIOS_DEBUG, "GPE0_STS: "); |
| 170 | for (i=31; i<= 16; i--) { |
| 171 | if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); |
| 172 | } |
| 173 | if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); |
| 174 | if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); |
| 175 | if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); |
| 176 | if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); |
| 177 | if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW "); |
| 178 | if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); |
| 179 | if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); |
| 180 | if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); |
| 181 | if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); |
| 182 | if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); |
| 183 | if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); |
| 184 | if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); |
| 185 | if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); |
| 186 | if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG "); |
| 187 | if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); |
| 188 | printk(BIOS_DEBUG, "\n"); |
| 189 | } |
| 190 | |
| 191 | |
| 192 | /** |
| 193 | * @brief read and clear TCOx_STS |
| 194 | * @return TCOx_STS registers |
| 195 | */ |
| 196 | static u32 reset_tco_status(void) |
| 197 | { |
| 198 | u32 tcobase = pmbase + 0x60; |
| 199 | u32 reg32; |
| 200 | |
| 201 | reg32 = inl(tcobase + 0x04); |
| 202 | /* set status bits are cleared by writing 1 to them */ |
| 203 | outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS |
| 204 | if (reg32 & (1 << 18)) |
| 205 | outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS |
| 206 | |
| 207 | return reg32; |
| 208 | } |
| 209 | |
| 210 | |
| 211 | static void dump_tco_status(u32 tco_sts) |
| 212 | { |
| 213 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 214 | if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); |
| 215 | if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); |
| 216 | if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); |
| 217 | if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); |
| 218 | if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); |
| 219 | if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); |
| 220 | if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); |
| 221 | if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); |
| 222 | if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); |
| 223 | if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); |
| 224 | if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); |
| 225 | if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); |
| 226 | if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); |
| 227 | printk(BIOS_DEBUG, "\n"); |
| 228 | } |
| 229 | |
| 230 | int southbridge_io_trap_handler(int smif) |
| 231 | { |
| 232 | switch (smif) { |
| 233 | case 0x32: |
| 234 | printk(BIOS_DEBUG, "OS Init\n"); |
| 235 | /* gnvs->smif: |
| 236 | * On success, the IO Trap Handler returns 0 |
| 237 | * On failure, the IO Trap Handler returns a value != 0 |
| 238 | */ |
| 239 | gnvs->smif = 0; |
| 240 | return 1; /* IO trap handled */ |
| 241 | } |
| 242 | |
| 243 | /* Not handled */ |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | /** |
| 248 | * @brief Set the EOS bit |
| 249 | */ |
| 250 | void southbridge_smi_set_eos(void) |
| 251 | { |
| 252 | u8 reg8; |
| 253 | |
| 254 | reg8 = inb(pmbase + SMI_EN); |
| 255 | reg8 |= EOS; |
| 256 | outb(reg8, pmbase + SMI_EN); |
| 257 | } |
| 258 | |
| 259 | static void busmaster_disable_on_bus(int bus) |
| 260 | { |
| 261 | int slot, func; |
| 262 | unsigned int val; |
| 263 | unsigned char hdr; |
| 264 | |
| 265 | for (slot = 0; slot < 0x20; slot++) { |
| 266 | for (func = 0; func < 8; func++) { |
| 267 | u32 reg32; |
| 268 | device_t dev = PCI_DEV(bus, slot, func); |
| 269 | |
| 270 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
| 271 | |
| 272 | if (val == 0xffffffff || val == 0x00000000 || |
| 273 | val == 0x0000ffff || val == 0xffff0000) |
| 274 | continue; |
| 275 | |
| 276 | /* Disable Bus Mastering for this one device */ |
| 277 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 278 | reg32 &= ~PCI_COMMAND_MASTER; |
| 279 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 280 | |
| 281 | /* If this is a bridge, then follow it. */ |
| 282 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 283 | hdr &= 0x7f; |
| 284 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
| 285 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
| 286 | unsigned int buses; |
| 287 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 288 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 289 | } |
| 290 | } |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | /* |
| 295 | * Drive GPIO 60 low to gate memory reset in S3. |
| 296 | * |
| 297 | * Intel reference designs all use GPIO 60 but it is |
| 298 | * not a requirement and boards could use a different pin. |
| 299 | */ |
| 300 | static void southbridge_gate_memory_reset(void) |
| 301 | { |
| 302 | u32 reg32; |
| 303 | u16 gpiobase; |
| 304 | |
| 305 | gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; |
| 306 | if (!gpiobase) |
| 307 | return; |
| 308 | |
| 309 | /* Make sure it is set as GPIO */ |
| 310 | reg32 = inl(gpiobase + GPIO_USE_SEL2); |
| 311 | if (!(reg32 & (1 << 28))) { |
| 312 | reg32 |= (1 << 28); |
| 313 | outl(reg32, gpiobase + GPIO_USE_SEL2); |
| 314 | } |
| 315 | |
| 316 | /* Make sure it is set as output */ |
| 317 | reg32 = inl(gpiobase + GP_IO_SEL2); |
| 318 | if (reg32 & (1 << 28)) { |
| 319 | reg32 &= ~(1 << 28); |
| 320 | outl(reg32, gpiobase + GP_IO_SEL2); |
| 321 | } |
| 322 | |
| 323 | /* Drive the output low */ |
| 324 | reg32 = inl(gpiobase + GP_LVL2); |
| 325 | reg32 &= ~(1 << 28); |
| 326 | outl(reg32, gpiobase + GP_LVL2); |
| 327 | } |
| 328 | |
| 329 | static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) |
| 330 | { |
| 331 | u8 reg8; |
| 332 | u32 reg32; |
| 333 | u8 slp_typ; |
| 334 | u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 335 | |
| 336 | // save and recover RTC port values |
| 337 | u8 tmp70, tmp72; |
| 338 | tmp70 = inb(0x70); |
| 339 | tmp72 = inb(0x72); |
| 340 | get_option(&s5pwr, "power_on_after_fail"); |
| 341 | outb(tmp70, 0x70); |
| 342 | outb(tmp72, 0x72); |
| 343 | |
| 344 | void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; |
| 345 | |
| 346 | /* First, disable further SMIs */ |
| 347 | reg8 = inb(pmbase + SMI_EN); |
| 348 | reg8 &= ~SLP_SMI_EN; |
| 349 | outb(reg8, pmbase + SMI_EN); |
| 350 | |
| 351 | /* Figure out SLP_TYP */ |
| 352 | reg32 = inl(pmbase + PM1_CNT); |
| 353 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
| 354 | slp_typ = (reg32 >> 10) & 7; |
| 355 | |
| 356 | /* Do any mainboard sleep handling */ |
| 357 | tseg_relocate((void **)&mainboard_sleep); |
| 358 | if (mainboard_sleep) |
| 359 | mainboard_sleep(slp_typ-2); |
| 360 | |
| 361 | #if CONFIG_ELOG_GSMI |
| 362 | /* Log S3, S4, and S5 entry */ |
| 363 | if (slp_typ >= 5) |
| 364 | elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); |
| 365 | #endif |
| 366 | |
| 367 | /* Next, do the deed. |
| 368 | */ |
| 369 | |
| 370 | switch (slp_typ) { |
| 371 | case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; |
| 372 | case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; |
| 373 | case 5: |
| 374 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 375 | |
| 376 | /* Gate memory reset */ |
| 377 | southbridge_gate_memory_reset(); |
| 378 | |
| 379 | /* Invalidate the cache before going to S3 */ |
| 380 | wbinvd(); |
| 381 | break; |
| 382 | case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; |
| 383 | case 7: |
| 384 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 385 | |
| 386 | outl(0, pmbase + GPE0_EN); |
| 387 | |
| 388 | /* Always set the flag in case CMOS was changed on runtime. For |
| 389 | * "KEEP", switch to "OFF" - KEEP is software emulated |
| 390 | */ |
| 391 | reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
| 392 | if (s5pwr == MAINBOARD_POWER_ON) { |
| 393 | reg8 &= ~1; |
| 394 | } else { |
| 395 | reg8 |= 1; |
| 396 | } |
| 397 | pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
| 398 | |
| 399 | /* also iterates over all bridges on bus 0 */ |
| 400 | busmaster_disable_on_bus(0); |
| 401 | break; |
| 402 | default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; |
| 403 | } |
| 404 | |
| 405 | /* Write back to the SLP register to cause the originally intended |
| 406 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 407 | * sleep happen. |
| 408 | */ |
| 409 | outl(reg32 | SLP_EN, pmbase + PM1_CNT); |
| 410 | |
| 411 | /* Make sure to stop executing code here for S3/S4/S5 */ |
| 412 | if (slp_typ > 1) |
| 413 | hlt(); |
| 414 | |
| 415 | /* In most sleep states, the code flow of this function ends at |
| 416 | * the line above. However, if we entered sleep state S1 and wake |
| 417 | * up again, we will continue to execute code in this function. |
| 418 | */ |
| 419 | reg32 = inl(pmbase + PM1_CNT); |
| 420 | if (reg32 & SCI_EN) { |
| 421 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 422 | reg32 &= ~(SLP_EN | SLP_TYP); |
| 423 | outl(reg32, pmbase + PM1_CNT); |
| 424 | } |
| 425 | } |
| 426 | |
| 427 | /* |
| 428 | * Look for Synchronous IO SMI and use save state from that |
| 429 | * core in case we are not running on the same core that |
| 430 | * initiated the IO transaction. |
| 431 | */ |
| 432 | /* FIXME: Confirm Haswell's SMM save state area structure. */ |
| 433 | static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) |
| 434 | { |
| 435 | em64t101_smm_state_save_area_t *state; |
| 436 | u32 base = smi_get_tseg_base() + 0x8000 + 0x7d00; |
| 437 | int node; |
| 438 | |
| 439 | /* Check all nodes looking for the one that issued the IO */ |
| 440 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 441 | state = (em64t101_smm_state_save_area_t *) |
| 442 | (base - (node * 0x400)); |
| 443 | |
| 444 | /* Check for Synchronous IO (bit0==1) */ |
| 445 | if (!(state->io_misc_info & (1 << 0))) |
| 446 | continue; |
| 447 | |
| 448 | /* Make sure it was a write (bit4==0) */ |
| 449 | if (state->io_misc_info & (1 << 4)) |
| 450 | continue; |
| 451 | |
| 452 | /* Check for APMC IO port */ |
| 453 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 454 | continue; |
| 455 | |
| 456 | /* Check AX against the requested command */ |
| 457 | if ((state->rax & 0xff) != cmd) |
| 458 | continue; |
| 459 | |
| 460 | return state; |
| 461 | } |
| 462 | |
| 463 | return NULL; |
| 464 | } |
| 465 | |
| 466 | #if CONFIG_ELOG_GSMI |
| 467 | static void southbridge_smi_gsmi(void) |
| 468 | { |
| 469 | u32 *ret, *param; |
| 470 | u8 sub_command; |
| 471 | em64t101_smm_state_save_area_t *io_smi = |
| 472 | smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); |
| 473 | |
| 474 | if (!io_smi) |
| 475 | return; |
| 476 | |
| 477 | /* Command and return value in EAX */ |
| 478 | ret = (u32*)&io_smi->rax; |
| 479 | sub_command = (u8)(*ret >> 8); |
| 480 | |
| 481 | /* Parameter buffer in EBX */ |
| 482 | param = (u32*)&io_smi->rbx; |
| 483 | |
| 484 | /* drivers/elog/gsmi.c */ |
| 485 | *ret = gsmi_exec(sub_command, param); |
| 486 | } |
| 487 | #endif |
| 488 | |
| 489 | static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) |
| 490 | { |
| 491 | u32 pmctrl; |
| 492 | u8 reg8; |
| 493 | int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; |
| 494 | em64t101_smm_state_save_area_t *state; |
| 495 | |
| 496 | /* Emulate B2 register as the FADT / Linux expects it */ |
| 497 | |
| 498 | reg8 = inb(APM_CNT); |
| 499 | switch (reg8) { |
| 500 | case APM_CNT_CST_CONTROL: |
| 501 | /* Calling this function seems to cause |
| 502 | * some kind of race condition in Linux |
| 503 | * and causes a kernel oops |
| 504 | */ |
| 505 | printk(BIOS_DEBUG, "C-state control\n"); |
| 506 | break; |
| 507 | case APM_CNT_PST_CONTROL: |
| 508 | /* Calling this function seems to cause |
| 509 | * some kind of race condition in Linux |
| 510 | * and causes a kernel oops |
| 511 | */ |
| 512 | printk(BIOS_DEBUG, "P-state control\n"); |
| 513 | break; |
| 514 | case APM_CNT_ACPI_DISABLE: |
| 515 | pmctrl = inl(pmbase + PM1_CNT); |
| 516 | pmctrl &= ~SCI_EN; |
| 517 | outl(pmctrl, pmbase + PM1_CNT); |
| 518 | printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); |
| 519 | break; |
| 520 | case APM_CNT_ACPI_ENABLE: |
| 521 | pmctrl = inl(pmbase + PM1_CNT); |
| 522 | pmctrl |= SCI_EN; |
| 523 | outl(pmctrl, pmbase + PM1_CNT); |
| 524 | printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); |
| 525 | break; |
| 526 | case APM_CNT_GNVS_UPDATE: |
| 527 | if (smm_initialized) { |
| 528 | printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); |
| 529 | return; |
| 530 | } |
| 531 | state = smi_apmc_find_state_save(reg8); |
| 532 | if (state) { |
| 533 | /* EBX in the state save contains the GNVS pointer */ |
| 534 | gnvs = (global_nvs_t *)((u32)state->rbx); |
| 535 | smm_initialized = 1; |
| 536 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
| 537 | } |
| 538 | break; |
| 539 | #if CONFIG_ELOG_GSMI |
| 540 | case ELOG_GSMI_APM_CNT: |
| 541 | southbridge_smi_gsmi(); |
| 542 | break; |
| 543 | #endif |
| 544 | } |
| 545 | |
| 546 | tseg_relocate((void **)&mainboard_apmc); |
| 547 | if (mainboard_apmc) |
| 548 | mainboard_apmc(reg8); |
| 549 | } |
| 550 | |
| 551 | static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) |
| 552 | { |
| 553 | u16 pm1_sts; |
| 554 | |
| 555 | pm1_sts = reset_pm1_status(); |
| 556 | dump_pm1_status(pm1_sts); |
| 557 | |
| 558 | /* While OSPM is not active, poweroff immediately |
| 559 | * on a power button event. |
| 560 | */ |
| 561 | if (pm1_sts & PWRBTN_STS) { |
| 562 | // power button pressed |
| 563 | u32 reg32; |
| 564 | reg32 = (7 << 10) | (1 << 13); |
| 565 | #if CONFIG_ELOG_GSMI |
| 566 | elog_add_event(ELOG_TYPE_POWER_BUTTON); |
| 567 | #endif |
| 568 | outl(reg32, pmbase + PM1_CNT); |
| 569 | } |
| 570 | } |
| 571 | |
| 572 | static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) |
| 573 | { |
| 574 | u32 gpe0_sts; |
| 575 | |
| 576 | gpe0_sts = reset_gpe0_status(); |
| 577 | dump_gpe0_status(gpe0_sts); |
| 578 | } |
| 579 | |
| 580 | static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) |
| 581 | { |
| 582 | void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi; |
| 583 | u16 reg16; |
| 584 | reg16 = inw(pmbase + ALT_GP_SMI_STS); |
| 585 | outw(reg16, pmbase + ALT_GP_SMI_STS); |
| 586 | |
| 587 | reg16 &= inw(pmbase + ALT_GP_SMI_EN); |
| 588 | |
| 589 | tseg_relocate((void **)&mainboard_gpi); |
| 590 | if (mainboard_gpi) { |
| 591 | mainboard_gpi(reg16); |
| 592 | } else { |
| 593 | if (reg16) |
| 594 | printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); |
| 595 | } |
| 596 | |
| 597 | outw(reg16, pmbase + ALT_GP_SMI_STS); |
| 598 | } |
| 599 | |
| 600 | static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) |
| 601 | { |
| 602 | u32 reg32; |
| 603 | |
| 604 | reg32 = inl(pmbase + SMI_EN); |
| 605 | |
| 606 | /* Are periodic SMIs enabled? */ |
| 607 | if ((reg32 & MCSMI_EN) == 0) |
| 608 | return; |
| 609 | |
| 610 | printk(BIOS_DEBUG, "Microcontroller SMI.\n"); |
| 611 | } |
| 612 | |
| 613 | |
| 614 | |
| 615 | static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) |
| 616 | { |
| 617 | u32 tco_sts; |
| 618 | |
| 619 | tco_sts = reset_tco_status(); |
| 620 | |
| 621 | /* Any TCO event? */ |
| 622 | if (!tco_sts) |
| 623 | return; |
| 624 | |
| 625 | if (tco_sts & (1 << 8)) { // BIOSWR |
| 626 | u8 bios_cntl; |
| 627 | |
| 628 | bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); |
| 629 | |
| 630 | if (bios_cntl & 1) { |
| 631 | /* BWE is RW, so the SMI was caused by a |
| 632 | * write to BWE, not by a write to the BIOS |
| 633 | */ |
| 634 | |
| 635 | /* This is the place where we notice someone |
| 636 | * is trying to tinker with the BIOS. We are |
| 637 | * trying to be nice and just ignore it. A more |
| 638 | * resolute answer would be to power down the |
| 639 | * box. |
| 640 | */ |
| 641 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
| 642 | pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); |
| 643 | } /* No else for now? */ |
| 644 | } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ |
| 645 | /* Handle TCO timeout */ |
| 646 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 647 | } else if (!tco_sts) { |
| 648 | dump_tco_status(tco_sts); |
| 649 | } |
| 650 | } |
| 651 | |
| 652 | static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) |
| 653 | { |
| 654 | u32 reg32; |
| 655 | |
| 656 | reg32 = inl(pmbase + SMI_EN); |
| 657 | |
| 658 | /* Are periodic SMIs enabled? */ |
| 659 | if ((reg32 & PERIODIC_EN) == 0) |
| 660 | return; |
| 661 | |
| 662 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 663 | } |
| 664 | |
| 665 | static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) |
| 666 | { |
| 667 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 668 | u32 trap_sts, trap_cycle; |
| 669 | u32 data, mask = 0; |
| 670 | int i; |
| 671 | |
| 672 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 673 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 674 | |
| 675 | trap_cycle = RCBA32(0x1e10); |
| 676 | for (i=16; i<20; i++) { |
| 677 | if (trap_cycle & (1 << i)) |
| 678 | mask |= (0xff << ((i - 16) << 2)); |
| 679 | } |
| 680 | |
| 681 | |
| 682 | /* IOTRAP(3) SMI function call */ |
| 683 | if (IOTRAP(3)) { |
| 684 | if (gnvs && gnvs->smif) |
| 685 | io_trap_handler(gnvs->smif); // call function smif |
| 686 | return; |
| 687 | } |
| 688 | |
| 689 | /* IOTRAP(2) currently unused |
| 690 | * IOTRAP(1) currently unused */ |
| 691 | |
| 692 | /* IOTRAP(0) SMIC */ |
| 693 | if (IOTRAP(0)) { |
| 694 | if (!(trap_cycle & (1 << 24))) { // It's a write |
| 695 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 696 | data = RCBA32(0x1e18); |
| 697 | data &= mask; |
| 698 | // if (smi1) |
| 699 | // southbridge_smi_command(data); |
| 700 | // return; |
| 701 | } |
| 702 | // Fall through to debug |
| 703 | } |
| 704 | |
| 705 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); |
| 706 | for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAPĀ = %d\n", i); |
| 707 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 708 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 709 | printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 710 | |
| 711 | if (!(trap_cycle & (1 << 24))) { |
| 712 | /* Write Cycle */ |
| 713 | data = RCBA32(0x1e18); |
| 714 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 715 | } |
| 716 | #undef IOTRAP |
| 717 | } |
| 718 | |
| 719 | typedef void (*smi_handler_t)(unsigned int node, |
| 720 | smm_state_save_area_t *state_save); |
| 721 | |
| 722 | static smi_handler_t southbridge_smi[32] = { |
| 723 | NULL, // [0] reserved |
| 724 | NULL, // [1] reserved |
| 725 | NULL, // [2] BIOS_STS |
| 726 | NULL, // [3] LEGACY_USB_STS |
| 727 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 728 | southbridge_smi_apmc, // [5] APM_STS |
| 729 | NULL, // [6] SWSMI_TMR_STS |
| 730 | NULL, // [7] reserved |
| 731 | southbridge_smi_pm1, // [8] PM1_STS |
| 732 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 733 | southbridge_smi_gpi, // [10] GPI_STS |
| 734 | southbridge_smi_mc, // [11] MCSMI_STS |
| 735 | NULL, // [12] DEVMON_STS |
| 736 | southbridge_smi_tco, // [13] TCO_STS |
| 737 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 738 | NULL, // [15] SERIRQ_SMI_STS |
| 739 | NULL, // [16] SMBUS_SMI_STS |
| 740 | NULL, // [17] LEGACY_USB2_STS |
| 741 | NULL, // [18] INTEL_USB2_STS |
| 742 | NULL, // [19] reserved |
| 743 | NULL, // [20] PCI_EXP_SMI_STS |
| 744 | southbridge_smi_monitor, // [21] MONITOR_STS |
| 745 | NULL, // [22] reserved |
| 746 | NULL, // [23] reserved |
| 747 | NULL, // [24] reserved |
| 748 | NULL, // [25] EL_SMI_STS |
| 749 | NULL, // [26] SPI_STS |
| 750 | NULL, // [27] reserved |
| 751 | NULL, // [28] reserved |
| 752 | NULL, // [29] reserved |
| 753 | NULL, // [30] reserved |
| 754 | NULL // [31] reserved |
| 755 | }; |
| 756 | |
| 757 | /** |
| 758 | * @brief Interrupt handler for SMI# |
| 759 | * |
| 760 | * @param smm_revision revision of the smm state save map |
| 761 | */ |
| 762 | |
| 763 | void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) |
| 764 | { |
| 765 | int i, dump = 0; |
| 766 | u32 smi_sts; |
| 767 | |
| 768 | /* Update global variable pmbase */ |
| 769 | pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; |
| 770 | |
| 771 | /* We need to clear the SMI status registers, or we won't see what's |
| 772 | * happening in the following calls. |
| 773 | */ |
| 774 | smi_sts = reset_smi_status(); |
| 775 | |
| 776 | /* Call SMI sub handler for each of the status bits */ |
| 777 | for (i = 0; i < 31; i++) { |
| 778 | if (smi_sts & (1 << i)) { |
| 779 | if (southbridge_smi[i]) { |
| 780 | #if CONFIG_SMM_TSEG |
| 781 | smi_handler_t handler = (smi_handler_t) |
| 782 | ((u8*)southbridge_smi[i] + |
| 783 | smi_get_tseg_base()); |
| 784 | if (handler) |
| 785 | handler(node, state_save); |
| 786 | #else |
| 787 | southbridge_smi[i](node, state_save); |
| 788 | #endif |
| 789 | } else { |
| 790 | printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " |
| 791 | "handler available.\n", i); |
| 792 | dump = 1; |
| 793 | } |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | if(dump) { |
| 798 | dump_smi_status(smi_sts); |
| 799 | } |
| 800 | |
| 801 | } |