Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
| 3 | #include <delay.h> |
| 4 | #include <types.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 5 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <cpu/x86/cache.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | e31ec29 | 2019-08-10 17:27:01 +0300 | [diff] [blame] | 12 | #include <cpu/intel/em64t101_save_state.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 13 | #include <spi-generic.h> |
| 14 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 15 | #include <halt.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 16 | #include <option.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 17 | #include <soc/lpc.h> |
| 18 | #include <soc/nvs.h> |
| 19 | #include <soc/pci_devs.h> |
| 20 | #include <soc/pm.h> |
| 21 | #include <soc/rcba.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 22 | #include <soc/xhci.h> |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 23 | #include <drivers/intel/gma/i915_reg.h> |
Matt DeVillier | 3a7a339 | 2018-12-25 22:22:47 -0600 | [diff] [blame] | 24 | #include <smmstore.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 25 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 26 | int southbridge_io_trap_handler(int smif) |
| 27 | { |
| 28 | switch (smif) { |
| 29 | case 0x32: |
| 30 | printk(BIOS_DEBUG, "OS Init\n"); |
| 31 | /* gnvs->smif: |
| 32 | * On success, the IO Trap Handler returns 0 |
| 33 | * On failure, the IO Trap Handler returns a value != 0 |
| 34 | */ |
| 35 | gnvs->smif = 0; |
| 36 | return 1; /* IO trap handled */ |
| 37 | } |
| 38 | |
| 39 | /* Not handled */ |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | /** |
| 44 | * @brief Set the EOS bit |
| 45 | */ |
| 46 | void southbridge_smi_set_eos(void) |
| 47 | { |
| 48 | enable_smi(EOS); |
| 49 | } |
| 50 | |
| 51 | static void busmaster_disable_on_bus(int bus) |
| 52 | { |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 53 | int slot, func; |
| 54 | unsigned int val; |
| 55 | unsigned char hdr; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 56 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 57 | for (slot = 0; slot < 0x20; slot++) { |
| 58 | for (func = 0; func < 8; func++) { |
Kyösti Mälkki | e16c9df | 2018-12-29 08:04:16 +0200 | [diff] [blame] | 59 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 60 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 61 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 62 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 63 | if (val == 0xffffffff || val == 0x00000000 || |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 64 | val == 0x0000ffff || val == 0xffff0000) |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 65 | continue; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 66 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 67 | /* Disable Bus Mastering for this one device */ |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 68 | pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 69 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 70 | /* If this is a bridge, then follow it. */ |
| 71 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 72 | hdr &= 0x7f; |
| 73 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 74 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 75 | unsigned int buses; |
| 76 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 77 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 78 | } |
| 79 | } |
| 80 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 81 | } |
| 82 | |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 83 | /* |
| 84 | * Turn off the backlight if it is on, and wait for the specified |
| 85 | * backlight off delay. This will allow panel power timings to meet |
| 86 | * spec and prevent brief garbage on the screen when turned off |
| 87 | * during firmware with power button triggered SMI. |
| 88 | */ |
| 89 | static void backlight_off(void) |
| 90 | { |
| 91 | void *reg_base; |
| 92 | uint32_t pp_ctrl; |
| 93 | uint32_t bl_off_delay; |
| 94 | |
Lee Leahy | 6ef5192 | 2017-03-17 10:56:08 -0700 | [diff] [blame] | 95 | reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD, |
| 96 | PCI_BASE_ADDRESS_0) & ~0xf); |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 97 | |
Patrick Rudolph | 9f8f115 | 2020-05-06 11:58:45 +0200 | [diff] [blame] | 98 | /* Validate pointer before using it */ |
| 99 | if (smm_points_to_smram(reg_base, PCH_PP_OFF_DELAYS + sizeof(uint32_t))) |
| 100 | return; |
| 101 | |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 102 | /* Check if backlight is enabled */ |
| 103 | pp_ctrl = read32(reg_base + PCH_PP_CONTROL); |
| 104 | if (!(pp_ctrl & EDP_BLC_ENABLE)) |
| 105 | return; |
| 106 | |
| 107 | /* Enable writes to this register */ |
| 108 | pp_ctrl &= ~PANEL_UNLOCK_MASK; |
| 109 | pp_ctrl |= PANEL_UNLOCK_REGS; |
| 110 | |
| 111 | /* Turn off backlight */ |
| 112 | pp_ctrl &= ~EDP_BLC_ENABLE; |
| 113 | |
| 114 | write32(reg_base + PCH_PP_CONTROL, pp_ctrl); |
| 115 | read32(reg_base + PCH_PP_CONTROL); |
| 116 | |
| 117 | /* Read backlight off delay in 100us units */ |
| 118 | bl_off_delay = read32(reg_base + PCH_PP_OFF_DELAYS); |
| 119 | bl_off_delay &= PANEL_LIGHT_OFF_DELAY_MASK; |
| 120 | bl_off_delay *= 100; |
| 121 | |
| 122 | /* Wait for backlight to turn off */ |
| 123 | udelay(bl_off_delay); |
| 124 | |
| 125 | printk(BIOS_INFO, "Backlight turned off\n"); |
| 126 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 127 | |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 128 | static int power_on_after_fail(void) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 129 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 130 | /* save and recover RTC port values */ |
| 131 | u8 tmp70, tmp72; |
| 132 | tmp70 = inb(0x70); |
| 133 | tmp72 = inb(0x72); |
Angel Pons | 88dcb31 | 2021-04-26 17:10:28 +0200 | [diff] [blame^] | 134 | const unsigned int s5pwr = get_uint_option("power_on_after_fail", |
Angel Pons | 62719a3 | 2021-04-19 13:15:28 +0200 | [diff] [blame] | 135 | CONFIG_MAINBOARD_POWER_FAILURE_STATE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 136 | outb(tmp70, 0x70); |
| 137 | outb(tmp72, 0x72); |
| 138 | |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 139 | /* For "KEEP", switch to "OFF" - KEEP is software emulated. */ |
| 140 | return (s5pwr == MAINBOARD_POWER_ON); |
| 141 | } |
| 142 | |
| 143 | static void southbridge_smi_sleep(void) |
| 144 | { |
| 145 | u32 reg32; |
| 146 | u8 slp_typ; |
| 147 | u16 pmbase = get_pmbase(); |
| 148 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 149 | /* First, disable further SMIs */ |
| 150 | disable_smi(SLP_SMI_EN); |
| 151 | |
| 152 | /* Figure out SLP_TYP */ |
Angel Pons | f92f273 | 2020-09-25 00:44:52 +0200 | [diff] [blame] | 153 | reg32 = inl(pmbase + PM1_CNT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 154 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 155 | slp_typ = acpi_sleep_from_pm1(reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 156 | |
| 157 | /* Do any mainboard sleep handling */ |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 158 | mainboard_smi_sleep(slp_typ); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 159 | |
| 160 | /* USB sleep preparations */ |
| 161 | usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); |
| 162 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 163 | /* Log S3, S4, and S5 entry */ |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 164 | if (slp_typ >= ACPI_S3) |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 165 | elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 166 | |
Duncan Laurie | d775dda | 2014-10-25 01:49:32 -0700 | [diff] [blame] | 167 | /* Clear pending GPE events */ |
| 168 | clear_gpe_status(); |
| 169 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 170 | /* Next, do the deed. |
| 171 | */ |
| 172 | |
| 173 | switch (slp_typ) { |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 174 | case ACPI_S0: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 175 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 176 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 177 | case ACPI_S1: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 178 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 179 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 180 | case ACPI_S3: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 181 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 182 | |
| 183 | /* Invalidate the cache before going to S3 */ |
| 184 | wbinvd(); |
| 185 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 186 | case ACPI_S4: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 187 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 188 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 189 | case ACPI_S5: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 190 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 191 | |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 192 | /* Turn off backlight if needed */ |
| 193 | backlight_off(); |
| 194 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 195 | /* Disable all GPE */ |
| 196 | disable_all_gpe(); |
| 197 | |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 198 | /* Always set the flag in case CMOS was changed on runtime. */ |
| 199 | if (power_on_after_fail()) |
| 200 | pci_and_config8(PCH_DEV_LPC, GEN_PMCON_3, ~1); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 201 | else |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 202 | pci_or_config8(PCH_DEV_LPC, GEN_PMCON_3, 1); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 203 | |
| 204 | /* also iterates over all bridges on bus 0 */ |
| 205 | busmaster_disable_on_bus(0); |
| 206 | break; |
| 207 | default: |
| 208 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 209 | break; |
| 210 | } |
| 211 | |
| 212 | /* |
| 213 | * Write back to the SLP register to cause the originally intended |
| 214 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 215 | * sleep happen. |
| 216 | */ |
| 217 | enable_pm1_control(SLP_EN); |
| 218 | |
| 219 | /* Make sure to stop executing code here for S3/S4/S5 */ |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 220 | if (slp_typ >= ACPI_S3) |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 221 | halt(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 222 | |
| 223 | /* |
| 224 | * In most sleep states, the code flow of this function ends at |
| 225 | * the line above. However, if we entered sleep state S1 and wake |
| 226 | * up again, we will continue to execute code in this function. |
| 227 | */ |
Angel Pons | f92f273 | 2020-09-25 00:44:52 +0200 | [diff] [blame] | 228 | reg32 = inl(pmbase + PM1_CNT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 229 | if (reg32 & SCI_EN) { |
| 230 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 231 | disable_pm1_control(SLP_EN | SLP_TYP); |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | /* |
| 236 | * Look for Synchronous IO SMI and use save state from that |
| 237 | * core in case we are not running on the same core that |
| 238 | * initiated the IO transaction. |
| 239 | */ |
| 240 | static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) |
| 241 | { |
| 242 | em64t101_smm_state_save_area_t *state; |
| 243 | int node; |
| 244 | |
| 245 | /* Check all nodes looking for the one that issued the IO */ |
| 246 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 247 | state = smm_get_save_state(node); |
| 248 | |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 249 | /* Check for Synchronous IO (bit0 == 1) */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 250 | if (!(state->io_misc_info & (1 << 0))) |
| 251 | continue; |
| 252 | |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 253 | /* Make sure it was a write (bit4 == 0) */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 254 | if (state->io_misc_info & (1 << 4)) |
| 255 | continue; |
| 256 | |
| 257 | /* Check for APMC IO port */ |
| 258 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 259 | continue; |
| 260 | |
| 261 | /* Check AX against the requested command */ |
| 262 | if ((state->rax & 0xff) != cmd) |
| 263 | continue; |
| 264 | |
| 265 | return state; |
| 266 | } |
| 267 | |
| 268 | return NULL; |
| 269 | } |
| 270 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 271 | static void southbridge_smi_gsmi(void) |
| 272 | { |
| 273 | u32 *ret, *param; |
| 274 | u8 sub_command; |
| 275 | em64t101_smm_state_save_area_t *io_smi = |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 276 | smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 277 | |
| 278 | if (!io_smi) |
| 279 | return; |
| 280 | |
| 281 | /* Command and return value in EAX */ |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 282 | ret = (u32 *)&io_smi->rax; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 283 | sub_command = (u8)(*ret >> 8); |
| 284 | |
| 285 | /* Parameter buffer in EBX */ |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 286 | param = (u32 *)&io_smi->rbx; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 287 | |
| 288 | /* drivers/elog/gsmi.c */ |
| 289 | *ret = gsmi_exec(sub_command, param); |
| 290 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 291 | |
Matt DeVillier | 3a7a339 | 2018-12-25 22:22:47 -0600 | [diff] [blame] | 292 | static void southbridge_smi_store(void) |
| 293 | { |
| 294 | u8 sub_command, ret; |
| 295 | em64t101_smm_state_save_area_t *io_smi = |
| 296 | smi_apmc_find_state_save(APM_CNT_SMMSTORE); |
| 297 | uint32_t reg_ebx; |
| 298 | |
| 299 | if (!io_smi) |
| 300 | return; |
| 301 | /* Command and return value in EAX */ |
| 302 | sub_command = (io_smi->rax >> 8) & 0xff; |
| 303 | |
| 304 | /* Parameter buffer in EBX */ |
| 305 | reg_ebx = io_smi->rbx; |
| 306 | |
| 307 | /* drivers/smmstore/smi.c */ |
| 308 | ret = smmstore_exec(sub_command, (void *)reg_ebx); |
| 309 | io_smi->rax = ret; |
| 310 | } |
| 311 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 312 | static void southbridge_smi_apmc(void) |
| 313 | { |
| 314 | u8 reg8; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 315 | |
Kyösti Mälkki | 9a1620f | 2021-01-08 13:27:33 +0200 | [diff] [blame] | 316 | reg8 = apm_get_apmc(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 317 | switch (reg8) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 318 | case APM_CNT_ACPI_DISABLE: |
| 319 | disable_pm1_control(SCI_EN); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 320 | break; |
| 321 | case APM_CNT_ACPI_ENABLE: |
| 322 | enable_pm1_control(SCI_EN); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 323 | break; |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 324 | case APM_CNT_ELOG_GSMI: |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 325 | if (CONFIG(ELOG_GSMI)) |
| 326 | southbridge_smi_gsmi(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 327 | break; |
Matt DeVillier | 3a7a339 | 2018-12-25 22:22:47 -0600 | [diff] [blame] | 328 | case APM_CNT_SMMSTORE: |
| 329 | if (CONFIG(SMMSTORE)) |
| 330 | southbridge_smi_store(); |
| 331 | break; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | mainboard_smi_apmc(reg8); |
| 335 | } |
| 336 | |
| 337 | static void southbridge_smi_pm1(void) |
| 338 | { |
| 339 | u16 pm1_sts = clear_pm1_status(); |
| 340 | |
| 341 | /* While OSPM is not active, poweroff immediately |
| 342 | * on a power button event. |
| 343 | */ |
| 344 | if (pm1_sts & PWRBTN_STS) { |
| 345 | /* power button pressed */ |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 346 | elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 347 | disable_pm1_control(-1UL); |
| 348 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | static void southbridge_smi_gpe0(void) |
| 353 | { |
| 354 | clear_gpe_status(); |
| 355 | } |
| 356 | |
| 357 | static void southbridge_smi_gpi(void) |
| 358 | { |
| 359 | mainboard_smi_gpi(clear_alt_smi_status()); |
| 360 | |
| 361 | /* Clear again after mainboard handler */ |
| 362 | clear_alt_smi_status(); |
| 363 | } |
| 364 | |
| 365 | static void southbridge_smi_mc(void) |
| 366 | { |
Angel Pons | f92f273 | 2020-09-25 00:44:52 +0200 | [diff] [blame] | 367 | u32 reg32 = inl(get_pmbase() + SMI_EN); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 368 | |
| 369 | /* Are microcontroller SMIs enabled? */ |
| 370 | if ((reg32 & MCSMI_EN) == 0) |
| 371 | return; |
| 372 | |
| 373 | printk(BIOS_DEBUG, "Microcontroller SMI.\n"); |
| 374 | } |
| 375 | |
| 376 | static void southbridge_smi_tco(void) |
| 377 | { |
| 378 | u32 tco_sts = clear_tco_status(); |
| 379 | |
| 380 | /* Any TCO event? */ |
| 381 | if (!tco_sts) |
| 382 | return; |
| 383 | |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 384 | // BIOSWR |
| 385 | if (tco_sts & (1 << 8)) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 386 | u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL); |
| 387 | |
| 388 | if (bios_cntl & 1) { |
| 389 | /* |
| 390 | * BWE is RW, so the SMI was caused by a |
| 391 | * write to BWE, not by a write to the BIOS |
| 392 | * |
| 393 | * This is the place where we notice someone |
| 394 | * is trying to tinker with the BIOS. We are |
| 395 | * trying to be nice and just ignore it. A more |
| 396 | * resolute answer would be to power down the |
| 397 | * box. |
| 398 | */ |
| 399 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 400 | pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, (bios_cntl & ~1)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 401 | } /* No else for now? */ |
| 402 | } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ |
| 403 | /* Handle TCO timeout */ |
| 404 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | static void southbridge_smi_periodic(void) |
| 409 | { |
Angel Pons | f92f273 | 2020-09-25 00:44:52 +0200 | [diff] [blame] | 410 | u32 reg32 = inl(get_pmbase() + SMI_EN); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 411 | |
| 412 | /* Are periodic SMIs enabled? */ |
| 413 | if ((reg32 & PERIODIC_EN) == 0) |
| 414 | return; |
| 415 | |
| 416 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 417 | } |
| 418 | |
| 419 | static void southbridge_smi_monitor(void) |
| 420 | { |
| 421 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 422 | u32 trap_sts, trap_cycle; |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 423 | u32 mask = 0; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 424 | int i; |
| 425 | |
| 426 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 427 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 428 | |
| 429 | trap_cycle = RCBA32(0x1e10); |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 430 | for (i = 16; i < 20; i++) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 431 | if (trap_cycle & (1 << i)) |
| 432 | mask |= (0xff << ((i - 16) << 2)); |
| 433 | } |
| 434 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 435 | /* IOTRAP(3) SMI function call */ |
| 436 | if (IOTRAP(3)) { |
| 437 | if (gnvs && gnvs->smif) |
| 438 | io_trap_handler(gnvs->smif); // call function smif |
| 439 | return; |
| 440 | } |
| 441 | |
| 442 | /* IOTRAP(2) currently unused |
| 443 | * IOTRAP(1) currently unused */ |
| 444 | |
| 445 | /* IOTRAP(0) SMIC */ |
| 446 | if (IOTRAP(0)) { |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 447 | // It's a write |
| 448 | if (!(trap_cycle & (1 << 24))) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 449 | printk(BIOS_DEBUG, "SMI1 command\n"); |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 450 | (void)RCBA32(0x1e18); |
| 451 | // data = RCBA32(0x1e18); |
| 452 | // data &= mask; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 453 | // if (smi1) |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 454 | // southbridge_smi_command(data); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 455 | // return; |
| 456 | } |
| 457 | // Fall through to debug |
| 458 | } |
| 459 | |
| 460 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", |
| 461 | trap_cycle & 0xfffc); |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 462 | for (i = 0; i < 4; i++) |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 463 | if (IOTRAP(i)) |
| 464 | printk(BIOS_DEBUG, " TRAP = %d\n", i); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 465 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 466 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 467 | printk(BIOS_DEBUG, " read/write: %s\n", |
| 468 | (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 469 | |
| 470 | if (!(trap_cycle & (1 << 24))) { |
| 471 | /* Write Cycle */ |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 472 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", RCBA32(0x1e18)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 473 | } |
| 474 | #undef IOTRAP |
| 475 | } |
| 476 | |
| 477 | typedef void (*smi_handler_t)(void); |
| 478 | |
| 479 | static smi_handler_t southbridge_smi[32] = { |
| 480 | NULL, // [0] reserved |
| 481 | NULL, // [1] reserved |
| 482 | NULL, // [2] BIOS_STS |
| 483 | NULL, // [3] LEGACY_USB_STS |
| 484 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 485 | southbridge_smi_apmc, // [5] APM_STS |
| 486 | NULL, // [6] SWSMI_TMR_STS |
| 487 | NULL, // [7] reserved |
| 488 | southbridge_smi_pm1, // [8] PM1_STS |
| 489 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 490 | southbridge_smi_gpi, // [10] GPI_STS |
| 491 | southbridge_smi_mc, // [11] MCSMI_STS |
| 492 | NULL, // [12] DEVMON_STS |
| 493 | southbridge_smi_tco, // [13] TCO_STS |
| 494 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 495 | NULL, // [15] SERIRQ_SMI_STS |
| 496 | NULL, // [16] SMBUS_SMI_STS |
| 497 | NULL, // [17] LEGACY_USB2_STS |
| 498 | NULL, // [18] INTEL_USB2_STS |
| 499 | NULL, // [19] reserved |
| 500 | NULL, // [20] PCI_EXP_SMI_STS |
| 501 | southbridge_smi_monitor, // [21] MONITOR_STS |
| 502 | NULL, // [22] reserved |
| 503 | NULL, // [23] reserved |
| 504 | NULL, // [24] reserved |
| 505 | NULL, // [25] EL_SMI_STS |
| 506 | NULL, // [26] SPI_STS |
| 507 | NULL, // [27] reserved |
| 508 | NULL, // [28] reserved |
| 509 | NULL, // [29] reserved |
| 510 | NULL, // [30] reserved |
| 511 | NULL // [31] reserved |
| 512 | }; |
| 513 | |
| 514 | /** |
| 515 | * @brief Interrupt handler for SMI# |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 516 | */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 517 | void southbridge_smi_handler(void) |
| 518 | { |
| 519 | int i; |
| 520 | u32 smi_sts; |
| 521 | |
| 522 | /* We need to clear the SMI status registers, or we won't see what's |
| 523 | * happening in the following calls. |
| 524 | */ |
| 525 | smi_sts = clear_smi_status(); |
| 526 | |
| 527 | /* Call SMI sub handler for each of the status bits */ |
| 528 | for (i = 0; i < 31; i++) { |
| 529 | if (smi_sts & (1 << i)) { |
| 530 | if (southbridge_smi[i]) { |
| 531 | southbridge_smi[i](); |
| 532 | } else { |
| 533 | printk(BIOS_DEBUG, |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 534 | "SMI_STS[%d] occurred, but no " |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 535 | "handler available.\n", i); |
| 536 | } |
| 537 | } |
| 538 | } |
| 539 | } |