soc/intel/broadwell: Use get_{pmbase,gpiobase}
This is to align Broadwell and Lynx Point.
Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45717
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 4a12d78..fd5d452 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -133,6 +133,7 @@
u32 reg32;
u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
+ u16 pmbase = get_pmbase();
/* save and recover RTC port values */
u8 tmp70, tmp72;
@@ -146,7 +147,7 @@
disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
- reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+ reg32 = inl(pmbase + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = acpi_sleep_from_pm1(reg32);
@@ -225,7 +226,7 @@
* the line above. However, if we entered sleep state S1 and wake
* up again, we will continue to execute code in this function.
*/
- reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+ reg32 = inl(pmbase + PM1_CNT);
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
disable_pm1_control(SLP_EN | SLP_TYP);
@@ -393,7 +394,7 @@
static void southbridge_smi_mc(void)
{
- u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);
+ u32 reg32 = inl(get_pmbase() + SMI_EN);
/* Are microcontroller SMIs enabled? */
if ((reg32 & MCSMI_EN) == 0)
@@ -436,7 +437,7 @@
static void southbridge_smi_periodic(void)
{
- u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);
+ u32 reg32 = inl(get_pmbase() + SMI_EN);
/* Are periodic SMIs enabled? */
if ((reg32 & PERIODIC_EN) == 0)