Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <delay.h> |
| 18 | #include <types.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 19 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame^] | 20 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <cpu/x86/cache.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <cpu/x86/smm.h> |
| 25 | #include <spi-generic.h> |
| 26 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 27 | #include <halt.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 28 | #include <pc80/mc146818rtc.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 29 | #include <soc/lpc.h> |
| 30 | #include <soc/nvs.h> |
| 31 | #include <soc/pci_devs.h> |
| 32 | #include <soc/pm.h> |
| 33 | #include <soc/rcba.h> |
| 34 | #include <soc/smm.h> |
| 35 | #include <soc/xhci.h> |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 36 | #include <drivers/intel/gma/i915_reg.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 37 | |
| 38 | static u8 smm_initialized = 0; |
| 39 | |
| 40 | /* |
| 41 | * GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located |
| 42 | * by coreboot. |
| 43 | */ |
| 44 | static global_nvs_t *gnvs; |
| 45 | global_nvs_t *smm_get_gnvs(void) |
| 46 | { |
| 47 | return gnvs; |
| 48 | } |
| 49 | |
| 50 | int southbridge_io_trap_handler(int smif) |
| 51 | { |
| 52 | switch (smif) { |
| 53 | case 0x32: |
| 54 | printk(BIOS_DEBUG, "OS Init\n"); |
| 55 | /* gnvs->smif: |
| 56 | * On success, the IO Trap Handler returns 0 |
| 57 | * On failure, the IO Trap Handler returns a value != 0 |
| 58 | */ |
| 59 | gnvs->smif = 0; |
| 60 | return 1; /* IO trap handled */ |
| 61 | } |
| 62 | |
| 63 | /* Not handled */ |
| 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | /** |
| 68 | * @brief Set the EOS bit |
| 69 | */ |
| 70 | void southbridge_smi_set_eos(void) |
| 71 | { |
| 72 | enable_smi(EOS); |
| 73 | } |
| 74 | |
| 75 | static void busmaster_disable_on_bus(int bus) |
| 76 | { |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 77 | int slot, func; |
| 78 | unsigned int val; |
| 79 | unsigned char hdr; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 80 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 81 | for (slot = 0; slot < 0x20; slot++) { |
| 82 | for (func = 0; func < 8; func++) { |
| 83 | u32 reg32; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 84 | |
Kyösti Mälkki | e16c9df | 2018-12-29 08:04:16 +0200 | [diff] [blame] | 85 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 86 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 87 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 88 | if (val == 0xffffffff || val == 0x00000000 || |
| 89 | val == 0x0000ffff || val == 0xffff0000) |
| 90 | continue; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 91 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 92 | /* Disable Bus Mastering for this one device */ |
| 93 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 94 | reg32 &= ~PCI_COMMAND_MASTER; |
| 95 | pci_write_config32(dev, PCI_COMMAND, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 96 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 97 | /* If this is a bridge, then follow it. */ |
| 98 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 99 | hdr &= 0x7f; |
| 100 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
| 101 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
| 102 | unsigned int buses; |
| 103 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 104 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 105 | } |
| 106 | } |
| 107 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 108 | } |
| 109 | |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 110 | /* |
| 111 | * Turn off the backlight if it is on, and wait for the specified |
| 112 | * backlight off delay. This will allow panel power timings to meet |
| 113 | * spec and prevent brief garbage on the screen when turned off |
| 114 | * during firmware with power button triggered SMI. |
| 115 | */ |
| 116 | static void backlight_off(void) |
| 117 | { |
| 118 | void *reg_base; |
| 119 | uint32_t pp_ctrl; |
| 120 | uint32_t bl_off_delay; |
| 121 | |
Lee Leahy | 6ef5192 | 2017-03-17 10:56:08 -0700 | [diff] [blame] | 122 | reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD, |
| 123 | PCI_BASE_ADDRESS_0) & ~0xf); |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 124 | |
| 125 | /* Check if backlight is enabled */ |
| 126 | pp_ctrl = read32(reg_base + PCH_PP_CONTROL); |
| 127 | if (!(pp_ctrl & EDP_BLC_ENABLE)) |
| 128 | return; |
| 129 | |
| 130 | /* Enable writes to this register */ |
| 131 | pp_ctrl &= ~PANEL_UNLOCK_MASK; |
| 132 | pp_ctrl |= PANEL_UNLOCK_REGS; |
| 133 | |
| 134 | /* Turn off backlight */ |
| 135 | pp_ctrl &= ~EDP_BLC_ENABLE; |
| 136 | |
| 137 | write32(reg_base + PCH_PP_CONTROL, pp_ctrl); |
| 138 | read32(reg_base + PCH_PP_CONTROL); |
| 139 | |
| 140 | /* Read backlight off delay in 100us units */ |
| 141 | bl_off_delay = read32(reg_base + PCH_PP_OFF_DELAYS); |
| 142 | bl_off_delay &= PANEL_LIGHT_OFF_DELAY_MASK; |
| 143 | bl_off_delay *= 100; |
| 144 | |
| 145 | /* Wait for backlight to turn off */ |
| 146 | udelay(bl_off_delay); |
| 147 | |
| 148 | printk(BIOS_INFO, "Backlight turned off\n"); |
| 149 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 150 | |
| 151 | static void southbridge_smi_sleep(void) |
| 152 | { |
| 153 | u8 reg8; |
| 154 | u32 reg32; |
| 155 | u8 slp_typ; |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 156 | u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 157 | |
| 158 | /* save and recover RTC port values */ |
| 159 | u8 tmp70, tmp72; |
| 160 | tmp70 = inb(0x70); |
| 161 | tmp72 = inb(0x72); |
| 162 | get_option(&s5pwr, "power_on_after_fail"); |
| 163 | outb(tmp70, 0x70); |
| 164 | outb(tmp72, 0x72); |
| 165 | |
| 166 | /* First, disable further SMIs */ |
| 167 | disable_smi(SLP_SMI_EN); |
| 168 | |
| 169 | /* Figure out SLP_TYP */ |
| 170 | reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 171 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 172 | slp_typ = acpi_sleep_from_pm1(reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 173 | |
| 174 | /* Do any mainboard sleep handling */ |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 175 | mainboard_smi_sleep(slp_typ); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 176 | |
| 177 | /* USB sleep preparations */ |
| 178 | usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); |
| 179 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 180 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 181 | /* Log S3, S4, and S5 entry */ |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 182 | if (slp_typ >= ACPI_S3) |
| 183 | elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 184 | #endif |
| 185 | |
Duncan Laurie | d775dda | 2014-10-25 01:49:32 -0700 | [diff] [blame] | 186 | /* Clear pending GPE events */ |
| 187 | clear_gpe_status(); |
| 188 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 189 | /* Next, do the deed. |
| 190 | */ |
| 191 | |
| 192 | switch (slp_typ) { |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 193 | case ACPI_S0: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 194 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 195 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 196 | case ACPI_S1: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 197 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 198 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 199 | case ACPI_S3: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 200 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 201 | |
| 202 | /* Invalidate the cache before going to S3 */ |
| 203 | wbinvd(); |
| 204 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 205 | case ACPI_S4: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 206 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 207 | break; |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 208 | case ACPI_S5: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 209 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 210 | |
Duncan Laurie | f3e0a13 | 2015-01-14 17:33:00 -0800 | [diff] [blame] | 211 | /* Turn off backlight if needed */ |
| 212 | backlight_off(); |
| 213 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 214 | /* Disable all GPE */ |
| 215 | disable_all_gpe(); |
| 216 | |
| 217 | /* Always set the flag in case CMOS was changed on runtime. For |
| 218 | * "KEEP", switch to "OFF" - KEEP is software emulated |
| 219 | */ |
| 220 | reg8 = pci_read_config8(PCH_DEV_LPC, GEN_PMCON_3); |
| 221 | if (s5pwr == MAINBOARD_POWER_ON) |
| 222 | reg8 &= ~1; |
| 223 | else |
| 224 | reg8 |= 1; |
| 225 | pci_write_config8(PCH_DEV_LPC, GEN_PMCON_3, reg8); |
| 226 | |
| 227 | /* also iterates over all bridges on bus 0 */ |
| 228 | busmaster_disable_on_bus(0); |
| 229 | break; |
| 230 | default: |
| 231 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 232 | break; |
| 233 | } |
| 234 | |
| 235 | /* |
| 236 | * Write back to the SLP register to cause the originally intended |
| 237 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 238 | * sleep happen. |
| 239 | */ |
| 240 | enable_pm1_control(SLP_EN); |
| 241 | |
| 242 | /* Make sure to stop executing code here for S3/S4/S5 */ |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 243 | if (slp_typ >= ACPI_S3) |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 244 | halt(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 245 | |
| 246 | /* |
| 247 | * In most sleep states, the code flow of this function ends at |
| 248 | * the line above. However, if we entered sleep state S1 and wake |
| 249 | * up again, we will continue to execute code in this function. |
| 250 | */ |
| 251 | reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 252 | if (reg32 & SCI_EN) { |
| 253 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 254 | disable_pm1_control(SLP_EN | SLP_TYP); |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | /* |
| 259 | * Look for Synchronous IO SMI and use save state from that |
| 260 | * core in case we are not running on the same core that |
| 261 | * initiated the IO transaction. |
| 262 | */ |
| 263 | static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) |
| 264 | { |
| 265 | em64t101_smm_state_save_area_t *state; |
| 266 | int node; |
| 267 | |
| 268 | /* Check all nodes looking for the one that issued the IO */ |
| 269 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 270 | state = smm_get_save_state(node); |
| 271 | |
| 272 | /* Check for Synchronous IO (bit0==1) */ |
| 273 | if (!(state->io_misc_info & (1 << 0))) |
| 274 | continue; |
| 275 | |
| 276 | /* Make sure it was a write (bit4==0) */ |
| 277 | if (state->io_misc_info & (1 << 4)) |
| 278 | continue; |
| 279 | |
| 280 | /* Check for APMC IO port */ |
| 281 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 282 | continue; |
| 283 | |
| 284 | /* Check AX against the requested command */ |
| 285 | if ((state->rax & 0xff) != cmd) |
| 286 | continue; |
| 287 | |
| 288 | return state; |
| 289 | } |
| 290 | |
| 291 | return NULL; |
| 292 | } |
| 293 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 294 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 295 | static void southbridge_smi_gsmi(void) |
| 296 | { |
| 297 | u32 *ret, *param; |
| 298 | u8 sub_command; |
| 299 | em64t101_smm_state_save_area_t *io_smi = |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 300 | smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 301 | |
| 302 | if (!io_smi) |
| 303 | return; |
| 304 | |
| 305 | /* Command and return value in EAX */ |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 306 | ret = (u32 *)&io_smi->rax; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 307 | sub_command = (u8)(*ret >> 8); |
| 308 | |
| 309 | /* Parameter buffer in EBX */ |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 310 | param = (u32 *)&io_smi->rbx; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 311 | |
| 312 | /* drivers/elog/gsmi.c */ |
| 313 | *ret = gsmi_exec(sub_command, param); |
| 314 | } |
| 315 | #endif |
| 316 | |
| 317 | static void finalize(void) |
| 318 | { |
| 319 | static int finalize_done; |
| 320 | |
| 321 | if (finalize_done) { |
| 322 | printk(BIOS_DEBUG, "SMM already finalized.\n"); |
| 323 | return; |
| 324 | } |
| 325 | finalize_done = 1; |
| 326 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 327 | #if IS_ENABLED(CONFIG_SPI_FLASH_SMM) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 328 | /* Re-init SPI driver to handle locked BAR */ |
| 329 | spi_init(); |
| 330 | #endif |
| 331 | } |
| 332 | |
| 333 | static void southbridge_smi_apmc(void) |
| 334 | { |
| 335 | u8 reg8; |
| 336 | em64t101_smm_state_save_area_t *state; |
| 337 | |
| 338 | /* Emulate B2 register as the FADT / Linux expects it */ |
| 339 | |
| 340 | reg8 = inb(APM_CNT); |
| 341 | switch (reg8) { |
| 342 | case APM_CNT_CST_CONTROL: |
| 343 | printk(BIOS_DEBUG, "C-state control\n"); |
| 344 | break; |
| 345 | case APM_CNT_PST_CONTROL: |
| 346 | printk(BIOS_DEBUG, "P-state control\n"); |
| 347 | break; |
| 348 | case APM_CNT_ACPI_DISABLE: |
| 349 | disable_pm1_control(SCI_EN); |
| 350 | printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); |
| 351 | break; |
| 352 | case APM_CNT_ACPI_ENABLE: |
| 353 | enable_pm1_control(SCI_EN); |
| 354 | printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); |
| 355 | break; |
| 356 | case APM_CNT_FINALIZE: |
| 357 | finalize(); |
| 358 | break; |
| 359 | case APM_CNT_GNVS_UPDATE: |
| 360 | if (smm_initialized) { |
| 361 | printk(BIOS_DEBUG, |
| 362 | "SMI#: SMM structures already initialized!\n"); |
| 363 | return; |
| 364 | } |
| 365 | state = smi_apmc_find_state_save(reg8); |
| 366 | if (state) { |
| 367 | /* EBX in the state save contains the GNVS pointer */ |
| 368 | gnvs = (global_nvs_t *)((u32)state->rbx); |
| 369 | smm_initialized = 1; |
| 370 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
| 371 | } |
| 372 | break; |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 373 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 374 | case APM_CNT_ELOG_GSMI: |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 375 | southbridge_smi_gsmi(); |
| 376 | break; |
| 377 | #endif |
| 378 | } |
| 379 | |
| 380 | mainboard_smi_apmc(reg8); |
| 381 | } |
| 382 | |
| 383 | static void southbridge_smi_pm1(void) |
| 384 | { |
| 385 | u16 pm1_sts = clear_pm1_status(); |
| 386 | |
| 387 | /* While OSPM is not active, poweroff immediately |
| 388 | * on a power button event. |
| 389 | */ |
| 390 | if (pm1_sts & PWRBTN_STS) { |
| 391 | /* power button pressed */ |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 392 | #if IS_ENABLED(CONFIG_ELOG_GSMI) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 393 | elog_add_event(ELOG_TYPE_POWER_BUTTON); |
| 394 | #endif |
| 395 | disable_pm1_control(-1UL); |
| 396 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | static void southbridge_smi_gpe0(void) |
| 401 | { |
| 402 | clear_gpe_status(); |
| 403 | } |
| 404 | |
| 405 | static void southbridge_smi_gpi(void) |
| 406 | { |
| 407 | mainboard_smi_gpi(clear_alt_smi_status()); |
| 408 | |
| 409 | /* Clear again after mainboard handler */ |
| 410 | clear_alt_smi_status(); |
| 411 | } |
| 412 | |
| 413 | static void southbridge_smi_mc(void) |
| 414 | { |
| 415 | u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 416 | |
| 417 | /* Are microcontroller SMIs enabled? */ |
| 418 | if ((reg32 & MCSMI_EN) == 0) |
| 419 | return; |
| 420 | |
| 421 | printk(BIOS_DEBUG, "Microcontroller SMI.\n"); |
| 422 | } |
| 423 | |
| 424 | static void southbridge_smi_tco(void) |
| 425 | { |
| 426 | u32 tco_sts = clear_tco_status(); |
| 427 | |
| 428 | /* Any TCO event? */ |
| 429 | if (!tco_sts) |
| 430 | return; |
| 431 | |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 432 | // BIOSWR |
| 433 | if (tco_sts & (1 << 8)) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 434 | u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL); |
| 435 | |
| 436 | if (bios_cntl & 1) { |
| 437 | /* |
| 438 | * BWE is RW, so the SMI was caused by a |
| 439 | * write to BWE, not by a write to the BIOS |
| 440 | * |
| 441 | * This is the place where we notice someone |
| 442 | * is trying to tinker with the BIOS. We are |
| 443 | * trying to be nice and just ignore it. A more |
| 444 | * resolute answer would be to power down the |
| 445 | * box. |
| 446 | */ |
| 447 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
| 448 | pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, |
| 449 | (bios_cntl & ~1)); |
| 450 | } /* No else for now? */ |
| 451 | } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ |
| 452 | /* Handle TCO timeout */ |
| 453 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | static void southbridge_smi_periodic(void) |
| 458 | { |
| 459 | u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 460 | |
| 461 | /* Are periodic SMIs enabled? */ |
| 462 | if ((reg32 & PERIODIC_EN) == 0) |
| 463 | return; |
| 464 | |
| 465 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 466 | } |
| 467 | |
| 468 | static void southbridge_smi_monitor(void) |
| 469 | { |
| 470 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 471 | u32 trap_sts, trap_cycle; |
| 472 | u32 data, mask = 0; |
| 473 | int i; |
| 474 | |
| 475 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 476 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 477 | |
| 478 | trap_cycle = RCBA32(0x1e10); |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 479 | for (i = 16; i < 20; i++) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 480 | if (trap_cycle & (1 << i)) |
| 481 | mask |= (0xff << ((i - 16) << 2)); |
| 482 | } |
| 483 | |
| 484 | |
| 485 | /* IOTRAP(3) SMI function call */ |
| 486 | if (IOTRAP(3)) { |
| 487 | if (gnvs && gnvs->smif) |
| 488 | io_trap_handler(gnvs->smif); // call function smif |
| 489 | return; |
| 490 | } |
| 491 | |
| 492 | /* IOTRAP(2) currently unused |
| 493 | * IOTRAP(1) currently unused */ |
| 494 | |
| 495 | /* IOTRAP(0) SMIC */ |
| 496 | if (IOTRAP(0)) { |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 497 | // It's a write |
| 498 | if (!(trap_cycle & (1 << 24))) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 499 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 500 | data = RCBA32(0x1e18); |
| 501 | data &= mask; |
| 502 | // if (smi1) |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 503 | // southbridge_smi_command(data); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 504 | // return; |
| 505 | } |
| 506 | // Fall through to debug |
| 507 | } |
| 508 | |
| 509 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", |
| 510 | trap_cycle & 0xfffc); |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 511 | for (i = 0; i < 4; i++) |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 512 | if (IOTRAP(i)) |
| 513 | printk(BIOS_DEBUG, " TRAP = %d\n", i); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 514 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 515 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 516 | printk(BIOS_DEBUG, " read/write: %s\n", |
| 517 | (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 518 | |
| 519 | if (!(trap_cycle & (1 << 24))) { |
| 520 | /* Write Cycle */ |
| 521 | data = RCBA32(0x1e18); |
| 522 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 523 | } |
| 524 | #undef IOTRAP |
| 525 | } |
| 526 | |
| 527 | typedef void (*smi_handler_t)(void); |
| 528 | |
| 529 | static smi_handler_t southbridge_smi[32] = { |
| 530 | NULL, // [0] reserved |
| 531 | NULL, // [1] reserved |
| 532 | NULL, // [2] BIOS_STS |
| 533 | NULL, // [3] LEGACY_USB_STS |
| 534 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 535 | southbridge_smi_apmc, // [5] APM_STS |
| 536 | NULL, // [6] SWSMI_TMR_STS |
| 537 | NULL, // [7] reserved |
| 538 | southbridge_smi_pm1, // [8] PM1_STS |
| 539 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 540 | southbridge_smi_gpi, // [10] GPI_STS |
| 541 | southbridge_smi_mc, // [11] MCSMI_STS |
| 542 | NULL, // [12] DEVMON_STS |
| 543 | southbridge_smi_tco, // [13] TCO_STS |
| 544 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 545 | NULL, // [15] SERIRQ_SMI_STS |
| 546 | NULL, // [16] SMBUS_SMI_STS |
| 547 | NULL, // [17] LEGACY_USB2_STS |
| 548 | NULL, // [18] INTEL_USB2_STS |
| 549 | NULL, // [19] reserved |
| 550 | NULL, // [20] PCI_EXP_SMI_STS |
| 551 | southbridge_smi_monitor, // [21] MONITOR_STS |
| 552 | NULL, // [22] reserved |
| 553 | NULL, // [23] reserved |
| 554 | NULL, // [24] reserved |
| 555 | NULL, // [25] EL_SMI_STS |
| 556 | NULL, // [26] SPI_STS |
| 557 | NULL, // [27] reserved |
| 558 | NULL, // [28] reserved |
| 559 | NULL, // [29] reserved |
| 560 | NULL, // [30] reserved |
| 561 | NULL // [31] reserved |
| 562 | }; |
| 563 | |
| 564 | /** |
| 565 | * @brief Interrupt handler for SMI# |
| 566 | * |
| 567 | * @param smm_revision revision of the smm state save map |
| 568 | */ |
| 569 | |
| 570 | void southbridge_smi_handler(void) |
| 571 | { |
| 572 | int i; |
| 573 | u32 smi_sts; |
| 574 | |
| 575 | /* We need to clear the SMI status registers, or we won't see what's |
| 576 | * happening in the following calls. |
| 577 | */ |
| 578 | smi_sts = clear_smi_status(); |
| 579 | |
| 580 | /* Call SMI sub handler for each of the status bits */ |
| 581 | for (i = 0; i < 31; i++) { |
| 582 | if (smi_sts & (1 << i)) { |
| 583 | if (southbridge_smi[i]) { |
| 584 | southbridge_smi[i](); |
| 585 | } else { |
| 586 | printk(BIOS_DEBUG, |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 587 | "SMI_STS[%d] occurred, but no " |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 588 | "handler available.\n", i); |
| 589 | } |
| 590 | } |
| 591 | } |
| 592 | } |