Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <delay.h> |
| 22 | #include <types.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 23 | #include <arch/io.h> |
| 24 | #include <console/console.h> |
| 25 | #include <cpu/x86/cache.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <cpu/x86/smm.h> |
| 28 | #include <spi-generic.h> |
| 29 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 30 | #include <halt.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 31 | #include <pc80/mc146818rtc.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame^] | 32 | #include <soc/lpc.h> |
| 33 | #include <soc/nvs.h> |
| 34 | #include <soc/pci_devs.h> |
| 35 | #include <soc/pm.h> |
| 36 | #include <soc/rcba.h> |
| 37 | #include <soc/smm.h> |
| 38 | #include <soc/xhci.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 39 | |
| 40 | static u8 smm_initialized = 0; |
| 41 | |
| 42 | /* |
| 43 | * GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located |
| 44 | * by coreboot. |
| 45 | */ |
| 46 | static global_nvs_t *gnvs; |
| 47 | global_nvs_t *smm_get_gnvs(void) |
| 48 | { |
| 49 | return gnvs; |
| 50 | } |
| 51 | |
| 52 | int southbridge_io_trap_handler(int smif) |
| 53 | { |
| 54 | switch (smif) { |
| 55 | case 0x32: |
| 56 | printk(BIOS_DEBUG, "OS Init\n"); |
| 57 | /* gnvs->smif: |
| 58 | * On success, the IO Trap Handler returns 0 |
| 59 | * On failure, the IO Trap Handler returns a value != 0 |
| 60 | */ |
| 61 | gnvs->smif = 0; |
| 62 | return 1; /* IO trap handled */ |
| 63 | } |
| 64 | |
| 65 | /* Not handled */ |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | /** |
| 70 | * @brief Set the EOS bit |
| 71 | */ |
| 72 | void southbridge_smi_set_eos(void) |
| 73 | { |
| 74 | enable_smi(EOS); |
| 75 | } |
| 76 | |
| 77 | static void busmaster_disable_on_bus(int bus) |
| 78 | { |
| 79 | int slot, func; |
| 80 | unsigned int val; |
| 81 | unsigned char hdr; |
| 82 | |
| 83 | for (slot = 0; slot < 0x20; slot++) { |
| 84 | for (func = 0; func < 8; func++) { |
| 85 | u32 reg32; |
| 86 | device_t dev = PCI_DEV(bus, slot, func); |
| 87 | |
| 88 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
| 89 | |
| 90 | if (val == 0xffffffff || val == 0x00000000 || |
| 91 | val == 0x0000ffff || val == 0xffff0000) |
| 92 | continue; |
| 93 | |
| 94 | /* Disable Bus Mastering for this one device */ |
| 95 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 96 | reg32 &= ~PCI_COMMAND_MASTER; |
| 97 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 98 | |
| 99 | /* If this is a bridge, then follow it. */ |
| 100 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 101 | hdr &= 0x7f; |
| 102 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
| 103 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
| 104 | unsigned int buses; |
| 105 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 106 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 107 | } |
| 108 | } |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | |
| 113 | static void southbridge_smi_sleep(void) |
| 114 | { |
| 115 | u8 reg8; |
| 116 | u32 reg32; |
| 117 | u8 slp_typ; |
| 118 | u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 119 | |
| 120 | /* save and recover RTC port values */ |
| 121 | u8 tmp70, tmp72; |
| 122 | tmp70 = inb(0x70); |
| 123 | tmp72 = inb(0x72); |
| 124 | get_option(&s5pwr, "power_on_after_fail"); |
| 125 | outb(tmp70, 0x70); |
| 126 | outb(tmp72, 0x72); |
| 127 | |
| 128 | /* First, disable further SMIs */ |
| 129 | disable_smi(SLP_SMI_EN); |
| 130 | |
| 131 | /* Figure out SLP_TYP */ |
| 132 | reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 133 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
| 134 | slp_typ = (reg32 >> 10) & 7; |
| 135 | |
| 136 | /* Do any mainboard sleep handling */ |
| 137 | mainboard_smi_sleep(slp_typ-2); |
| 138 | |
| 139 | /* USB sleep preparations */ |
| 140 | usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); |
| 141 | |
| 142 | #if CONFIG_ELOG_GSMI |
| 143 | /* Log S3, S4, and S5 entry */ |
| 144 | if (slp_typ >= 5) |
| 145 | elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); |
| 146 | #endif |
| 147 | |
Duncan Laurie | d775dda | 2014-10-25 01:49:32 -0700 | [diff] [blame] | 148 | /* Clear pending GPE events */ |
| 149 | clear_gpe_status(); |
| 150 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 151 | /* Next, do the deed. |
| 152 | */ |
| 153 | |
| 154 | switch (slp_typ) { |
| 155 | case SLP_TYP_S0: |
| 156 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 157 | break; |
| 158 | case SLP_TYP_S1: |
| 159 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 160 | break; |
| 161 | case SLP_TYP_S3: |
| 162 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 163 | |
| 164 | /* Invalidate the cache before going to S3 */ |
| 165 | wbinvd(); |
| 166 | break; |
| 167 | case SLP_TYP_S4: |
| 168 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 169 | break; |
| 170 | case SLP_TYP_S5: |
| 171 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 172 | |
| 173 | /* Disable all GPE */ |
| 174 | disable_all_gpe(); |
| 175 | |
| 176 | /* Always set the flag in case CMOS was changed on runtime. For |
| 177 | * "KEEP", switch to "OFF" - KEEP is software emulated |
| 178 | */ |
| 179 | reg8 = pci_read_config8(PCH_DEV_LPC, GEN_PMCON_3); |
| 180 | if (s5pwr == MAINBOARD_POWER_ON) |
| 181 | reg8 &= ~1; |
| 182 | else |
| 183 | reg8 |= 1; |
| 184 | pci_write_config8(PCH_DEV_LPC, GEN_PMCON_3, reg8); |
| 185 | |
| 186 | /* also iterates over all bridges on bus 0 */ |
| 187 | busmaster_disable_on_bus(0); |
| 188 | break; |
| 189 | default: |
| 190 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 191 | break; |
| 192 | } |
| 193 | |
| 194 | /* |
| 195 | * Write back to the SLP register to cause the originally intended |
| 196 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 197 | * sleep happen. |
| 198 | */ |
| 199 | enable_pm1_control(SLP_EN); |
| 200 | |
| 201 | /* Make sure to stop executing code here for S3/S4/S5 */ |
| 202 | if (slp_typ > 1) |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 203 | halt(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 204 | |
| 205 | /* |
| 206 | * In most sleep states, the code flow of this function ends at |
| 207 | * the line above. However, if we entered sleep state S1 and wake |
| 208 | * up again, we will continue to execute code in this function. |
| 209 | */ |
| 210 | reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 211 | if (reg32 & SCI_EN) { |
| 212 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 213 | disable_pm1_control(SLP_EN | SLP_TYP); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * Look for Synchronous IO SMI and use save state from that |
| 219 | * core in case we are not running on the same core that |
| 220 | * initiated the IO transaction. |
| 221 | */ |
| 222 | static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) |
| 223 | { |
| 224 | em64t101_smm_state_save_area_t *state; |
| 225 | int node; |
| 226 | |
| 227 | /* Check all nodes looking for the one that issued the IO */ |
| 228 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 229 | state = smm_get_save_state(node); |
| 230 | |
| 231 | /* Check for Synchronous IO (bit0==1) */ |
| 232 | if (!(state->io_misc_info & (1 << 0))) |
| 233 | continue; |
| 234 | |
| 235 | /* Make sure it was a write (bit4==0) */ |
| 236 | if (state->io_misc_info & (1 << 4)) |
| 237 | continue; |
| 238 | |
| 239 | /* Check for APMC IO port */ |
| 240 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 241 | continue; |
| 242 | |
| 243 | /* Check AX against the requested command */ |
| 244 | if ((state->rax & 0xff) != cmd) |
| 245 | continue; |
| 246 | |
| 247 | return state; |
| 248 | } |
| 249 | |
| 250 | return NULL; |
| 251 | } |
| 252 | |
| 253 | #if CONFIG_ELOG_GSMI |
| 254 | static void southbridge_smi_gsmi(void) |
| 255 | { |
| 256 | u32 *ret, *param; |
| 257 | u8 sub_command; |
| 258 | em64t101_smm_state_save_area_t *io_smi = |
| 259 | smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); |
| 260 | |
| 261 | if (!io_smi) |
| 262 | return; |
| 263 | |
| 264 | /* Command and return value in EAX */ |
| 265 | ret = (u32*)&io_smi->rax; |
| 266 | sub_command = (u8)(*ret >> 8); |
| 267 | |
| 268 | /* Parameter buffer in EBX */ |
| 269 | param = (u32*)&io_smi->rbx; |
| 270 | |
| 271 | /* drivers/elog/gsmi.c */ |
| 272 | *ret = gsmi_exec(sub_command, param); |
| 273 | } |
| 274 | #endif |
| 275 | |
| 276 | static void finalize(void) |
| 277 | { |
| 278 | static int finalize_done; |
| 279 | |
| 280 | if (finalize_done) { |
| 281 | printk(BIOS_DEBUG, "SMM already finalized.\n"); |
| 282 | return; |
| 283 | } |
| 284 | finalize_done = 1; |
| 285 | |
| 286 | #if CONFIG_SPI_FLASH_SMM |
| 287 | /* Re-init SPI driver to handle locked BAR */ |
| 288 | spi_init(); |
| 289 | #endif |
| 290 | } |
| 291 | |
| 292 | static void southbridge_smi_apmc(void) |
| 293 | { |
| 294 | u8 reg8; |
| 295 | em64t101_smm_state_save_area_t *state; |
| 296 | |
| 297 | /* Emulate B2 register as the FADT / Linux expects it */ |
| 298 | |
| 299 | reg8 = inb(APM_CNT); |
| 300 | switch (reg8) { |
| 301 | case APM_CNT_CST_CONTROL: |
| 302 | printk(BIOS_DEBUG, "C-state control\n"); |
| 303 | break; |
| 304 | case APM_CNT_PST_CONTROL: |
| 305 | printk(BIOS_DEBUG, "P-state control\n"); |
| 306 | break; |
| 307 | case APM_CNT_ACPI_DISABLE: |
| 308 | disable_pm1_control(SCI_EN); |
| 309 | printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); |
| 310 | break; |
| 311 | case APM_CNT_ACPI_ENABLE: |
| 312 | enable_pm1_control(SCI_EN); |
| 313 | printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); |
| 314 | break; |
| 315 | case APM_CNT_FINALIZE: |
| 316 | finalize(); |
| 317 | break; |
| 318 | case APM_CNT_GNVS_UPDATE: |
| 319 | if (smm_initialized) { |
| 320 | printk(BIOS_DEBUG, |
| 321 | "SMI#: SMM structures already initialized!\n"); |
| 322 | return; |
| 323 | } |
| 324 | state = smi_apmc_find_state_save(reg8); |
| 325 | if (state) { |
| 326 | /* EBX in the state save contains the GNVS pointer */ |
| 327 | gnvs = (global_nvs_t *)((u32)state->rbx); |
| 328 | smm_initialized = 1; |
| 329 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
| 330 | } |
| 331 | break; |
| 332 | #if CONFIG_ELOG_GSMI |
| 333 | case ELOG_GSMI_APM_CNT: |
| 334 | southbridge_smi_gsmi(); |
| 335 | break; |
| 336 | #endif |
| 337 | } |
| 338 | |
| 339 | mainboard_smi_apmc(reg8); |
| 340 | } |
| 341 | |
| 342 | static void southbridge_smi_pm1(void) |
| 343 | { |
| 344 | u16 pm1_sts = clear_pm1_status(); |
| 345 | |
| 346 | /* While OSPM is not active, poweroff immediately |
| 347 | * on a power button event. |
| 348 | */ |
| 349 | if (pm1_sts & PWRBTN_STS) { |
| 350 | /* power button pressed */ |
| 351 | #if CONFIG_ELOG_GSMI |
| 352 | elog_add_event(ELOG_TYPE_POWER_BUTTON); |
| 353 | #endif |
| 354 | disable_pm1_control(-1UL); |
| 355 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | static void southbridge_smi_gpe0(void) |
| 360 | { |
| 361 | clear_gpe_status(); |
| 362 | } |
| 363 | |
| 364 | static void southbridge_smi_gpi(void) |
| 365 | { |
| 366 | mainboard_smi_gpi(clear_alt_smi_status()); |
| 367 | |
| 368 | /* Clear again after mainboard handler */ |
| 369 | clear_alt_smi_status(); |
| 370 | } |
| 371 | |
| 372 | static void southbridge_smi_mc(void) |
| 373 | { |
| 374 | u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 375 | |
| 376 | /* Are microcontroller SMIs enabled? */ |
| 377 | if ((reg32 & MCSMI_EN) == 0) |
| 378 | return; |
| 379 | |
| 380 | printk(BIOS_DEBUG, "Microcontroller SMI.\n"); |
| 381 | } |
| 382 | |
| 383 | static void southbridge_smi_tco(void) |
| 384 | { |
| 385 | u32 tco_sts = clear_tco_status(); |
| 386 | |
| 387 | /* Any TCO event? */ |
| 388 | if (!tco_sts) |
| 389 | return; |
| 390 | |
| 391 | if (tco_sts & (1 << 8)) { // BIOSWR |
| 392 | u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL); |
| 393 | |
| 394 | if (bios_cntl & 1) { |
| 395 | /* |
| 396 | * BWE is RW, so the SMI was caused by a |
| 397 | * write to BWE, not by a write to the BIOS |
| 398 | * |
| 399 | * This is the place where we notice someone |
| 400 | * is trying to tinker with the BIOS. We are |
| 401 | * trying to be nice and just ignore it. A more |
| 402 | * resolute answer would be to power down the |
| 403 | * box. |
| 404 | */ |
| 405 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
| 406 | pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, |
| 407 | (bios_cntl & ~1)); |
| 408 | } /* No else for now? */ |
| 409 | } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ |
| 410 | /* Handle TCO timeout */ |
| 411 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | static void southbridge_smi_periodic(void) |
| 416 | { |
| 417 | u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 418 | |
| 419 | /* Are periodic SMIs enabled? */ |
| 420 | if ((reg32 & PERIODIC_EN) == 0) |
| 421 | return; |
| 422 | |
| 423 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 424 | } |
| 425 | |
| 426 | static void southbridge_smi_monitor(void) |
| 427 | { |
| 428 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 429 | u32 trap_sts, trap_cycle; |
| 430 | u32 data, mask = 0; |
| 431 | int i; |
| 432 | |
| 433 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 434 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 435 | |
| 436 | trap_cycle = RCBA32(0x1e10); |
| 437 | for (i=16; i<20; i++) { |
| 438 | if (trap_cycle & (1 << i)) |
| 439 | mask |= (0xff << ((i - 16) << 2)); |
| 440 | } |
| 441 | |
| 442 | |
| 443 | /* IOTRAP(3) SMI function call */ |
| 444 | if (IOTRAP(3)) { |
| 445 | if (gnvs && gnvs->smif) |
| 446 | io_trap_handler(gnvs->smif); // call function smif |
| 447 | return; |
| 448 | } |
| 449 | |
| 450 | /* IOTRAP(2) currently unused |
| 451 | * IOTRAP(1) currently unused */ |
| 452 | |
| 453 | /* IOTRAP(0) SMIC */ |
| 454 | if (IOTRAP(0)) { |
| 455 | if (!(trap_cycle & (1 << 24))) { // It's a write |
| 456 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 457 | data = RCBA32(0x1e18); |
| 458 | data &= mask; |
| 459 | // if (smi1) |
| 460 | // southbridge_smi_command(data); |
| 461 | // return; |
| 462 | } |
| 463 | // Fall through to debug |
| 464 | } |
| 465 | |
| 466 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", |
| 467 | trap_cycle & 0xfffc); |
| 468 | for (i=0; i < 4; i++) |
| 469 | if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); |
| 470 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 471 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 472 | printk(BIOS_DEBUG, " read/write: %s\n", |
| 473 | (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 474 | |
| 475 | if (!(trap_cycle & (1 << 24))) { |
| 476 | /* Write Cycle */ |
| 477 | data = RCBA32(0x1e18); |
| 478 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 479 | } |
| 480 | #undef IOTRAP |
| 481 | } |
| 482 | |
| 483 | typedef void (*smi_handler_t)(void); |
| 484 | |
| 485 | static smi_handler_t southbridge_smi[32] = { |
| 486 | NULL, // [0] reserved |
| 487 | NULL, // [1] reserved |
| 488 | NULL, // [2] BIOS_STS |
| 489 | NULL, // [3] LEGACY_USB_STS |
| 490 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 491 | southbridge_smi_apmc, // [5] APM_STS |
| 492 | NULL, // [6] SWSMI_TMR_STS |
| 493 | NULL, // [7] reserved |
| 494 | southbridge_smi_pm1, // [8] PM1_STS |
| 495 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 496 | southbridge_smi_gpi, // [10] GPI_STS |
| 497 | southbridge_smi_mc, // [11] MCSMI_STS |
| 498 | NULL, // [12] DEVMON_STS |
| 499 | southbridge_smi_tco, // [13] TCO_STS |
| 500 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 501 | NULL, // [15] SERIRQ_SMI_STS |
| 502 | NULL, // [16] SMBUS_SMI_STS |
| 503 | NULL, // [17] LEGACY_USB2_STS |
| 504 | NULL, // [18] INTEL_USB2_STS |
| 505 | NULL, // [19] reserved |
| 506 | NULL, // [20] PCI_EXP_SMI_STS |
| 507 | southbridge_smi_monitor, // [21] MONITOR_STS |
| 508 | NULL, // [22] reserved |
| 509 | NULL, // [23] reserved |
| 510 | NULL, // [24] reserved |
| 511 | NULL, // [25] EL_SMI_STS |
| 512 | NULL, // [26] SPI_STS |
| 513 | NULL, // [27] reserved |
| 514 | NULL, // [28] reserved |
| 515 | NULL, // [29] reserved |
| 516 | NULL, // [30] reserved |
| 517 | NULL // [31] reserved |
| 518 | }; |
| 519 | |
| 520 | /** |
| 521 | * @brief Interrupt handler for SMI# |
| 522 | * |
| 523 | * @param smm_revision revision of the smm state save map |
| 524 | */ |
| 525 | |
| 526 | void southbridge_smi_handler(void) |
| 527 | { |
| 528 | int i; |
| 529 | u32 smi_sts; |
| 530 | |
| 531 | /* We need to clear the SMI status registers, or we won't see what's |
| 532 | * happening in the following calls. |
| 533 | */ |
| 534 | smi_sts = clear_smi_status(); |
| 535 | |
| 536 | /* Call SMI sub handler for each of the status bits */ |
| 537 | for (i = 0; i < 31; i++) { |
| 538 | if (smi_sts & (1 << i)) { |
| 539 | if (southbridge_smi[i]) { |
| 540 | southbridge_smi[i](); |
| 541 | } else { |
| 542 | printk(BIOS_DEBUG, |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 543 | "SMI_STS[%d] occurred, but no " |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 544 | "handler available.\n", i); |
| 545 | } |
| 546 | } |
| 547 | } |
| 548 | } |