Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 2 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
| 7 | #include <acpi/acpi_ivrs.h> |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Elyes HAOUAS | 146d0c2 | 2020-07-22 11:47:08 +0200 | [diff] [blame] | 9 | #include <types.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 13 | #include <string.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 14 | #include <stdlib.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 15 | #include <lib.h> |
| 16 | #include <cpu/cpu.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 17 | #include <Porting.h> |
| 18 | #include <AGESA.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 19 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 20 | #include <cpu/x86/lapic.h> |
| 21 | #include <cpu/amd/msr.h> |
| 22 | #include <cpu/amd/mtrr.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 23 | #include <acpi/acpigen.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 24 | #include <northbridge/amd/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 25 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 26 | #include <southbridge/amd/pi/hudson/pci_devs.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 27 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 28 | #define MAX_NODE_NUMS MAX_NODES |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 29 | #define PCIE_CAP_AER BIT(5) |
| 30 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 31 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 32 | typedef struct dram_base_mask { |
| 33 | u32 base; //[47:27] at [28:8] |
| 34 | u32 mask; //[47:27] at [28:8] and enable at bit 0 |
| 35 | } dram_base_mask_t; |
| 36 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 37 | static unsigned int node_nums; |
| 38 | static unsigned int sblink; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 39 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 40 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 41 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 42 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 43 | static unsigned int fx_devs = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 44 | |
| 45 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 46 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 47 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 48 | dram_base_mask_t d; |
| 49 | dev = __f1_dev[0]; |
| 50 | u32 temp; |
| 51 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 52 | d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too |
| 53 | temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 54 | d.mask |= temp<<21; |
| 55 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 56 | d.mask |= (temp & 1); // enable bit |
| 57 | d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too |
| 58 | temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 59 | d.base |= temp<<21; |
| 60 | return d; |
| 61 | } |
| 62 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 63 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 64 | u32 io_min, u32 io_max) |
| 65 | { |
| 66 | u32 i; |
| 67 | u32 tempreg; |
| 68 | /* io range allocation */ |
| 69 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 70 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 71 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 72 | tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 73 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 74 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 75 | } |
| 76 | |
| 77 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 78 | { |
| 79 | u32 i; |
| 80 | u32 tempreg; |
| 81 | /* io range allocation */ |
| 82 | tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 83 | for (i = 0; i < nodes; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 84 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 85 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 86 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 87 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 88 | } |
| 89 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 90 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 91 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 92 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | static void get_fx_devs(void) |
| 96 | { |
| 97 | int i; |
| 98 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 99 | __f0_dev[i] = get_node_pci(i, 0); |
| 100 | __f1_dev[i] = get_node_pci(i, 1); |
| 101 | __f2_dev[i] = get_node_pci(i, 2); |
| 102 | __f4_dev[i] = get_node_pci(i, 4); |
| 103 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 104 | fx_devs = i+1; |
| 105 | } |
| 106 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 107 | die("Cannot find 0:0x18.[0|1]\n"); |
| 108 | } |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 109 | printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 110 | } |
| 111 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 112 | static u32 f1_read_config32(unsigned int reg) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 113 | { |
| 114 | if (fx_devs == 0) |
| 115 | get_fx_devs(); |
| 116 | return pci_read_config32(__f1_dev[0], reg); |
| 117 | } |
| 118 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 119 | static void f1_write_config32(unsigned int reg, u32 value) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 120 | { |
| 121 | int i; |
| 122 | if (fx_devs == 0) |
| 123 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 124 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 125 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 126 | dev = __f1_dev[i]; |
| 127 | if (dev && dev->enabled) { |
| 128 | pci_write_config32(dev, reg, value); |
| 129 | } |
| 130 | } |
| 131 | } |
| 132 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 133 | static u32 amdfam16_nodeid(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 134 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 135 | return (dev->path.pci.devfn >> 3) - DEV_CDB; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 139 | { |
| 140 | u32 val; |
| 141 | |
| 142 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 143 | /* it will routing |
| 144 | * (1)mmio 0xa0000:0xbffff |
| 145 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 146 | */ |
| 147 | f1_write_config32(0xf4, val); |
| 148 | |
| 149 | } |
| 150 | |
| 151 | /** |
| 152 | * @return |
Elyes HAOUAS | 99b075a | 2019-12-30 14:29:31 +0100 | [diff] [blame] | 153 | * @retval 2 resource does not exist, usable |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 154 | * @retval 0 resource exists, not usable |
| 155 | * @retval 1 resource exist, resource has been allocated before |
| 156 | */ |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 157 | static int reg_useable(unsigned int reg, struct device *goal_dev, |
| 158 | unsigned int goal_nodeid, unsigned int goal_link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 159 | { |
| 160 | struct resource *res; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 161 | unsigned int nodeid, link = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 162 | int result; |
| 163 | res = 0; |
| 164 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 165 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 166 | dev = __f0_dev[nodeid]; |
| 167 | if (!dev) |
| 168 | continue; |
| 169 | for (link = 0; !res && (link < 8); link++) { |
| 170 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 171 | } |
| 172 | } |
| 173 | result = 2; |
| 174 | if (res) { |
| 175 | result = 0; |
| 176 | if ((goal_link == (link - 1)) && |
| 177 | (goal_nodeid == (nodeid - 1)) && |
| 178 | (res->flags <= 1)) { |
| 179 | result = 1; |
| 180 | } |
| 181 | } |
| 182 | return result; |
| 183 | } |
| 184 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 185 | static struct resource *amdfam16_find_iopair(struct device *dev, |
| 186 | unsigned int nodeid, unsigned int link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 187 | { |
| 188 | struct resource *resource; |
| 189 | u32 free_reg, reg; |
| 190 | resource = 0; |
| 191 | free_reg = 0; |
| 192 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 193 | int result; |
| 194 | result = reg_useable(reg, dev, nodeid, link); |
| 195 | if (result == 1) { |
| 196 | /* I have been allocated this one */ |
| 197 | break; |
| 198 | } |
| 199 | else if (result > 1) { |
| 200 | /* I have a free register pair */ |
| 201 | free_reg = reg; |
| 202 | } |
| 203 | } |
| 204 | if (reg > 0xd8) { |
| 205 | reg = free_reg; // if no free, the free_reg still be 0 |
| 206 | } |
| 207 | |
| 208 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 209 | |
| 210 | return resource; |
| 211 | } |
| 212 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 213 | static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 214 | { |
| 215 | struct resource *resource; |
| 216 | u32 free_reg, reg; |
| 217 | resource = 0; |
| 218 | free_reg = 0; |
| 219 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 220 | int result; |
| 221 | result = reg_useable(reg, dev, nodeid, link); |
| 222 | if (result == 1) { |
| 223 | /* I have been allocated this one */ |
| 224 | break; |
| 225 | } |
| 226 | else if (result > 1) { |
| 227 | /* I have a free register pair */ |
| 228 | free_reg = reg; |
| 229 | } |
| 230 | } |
| 231 | if (reg > 0xb8) { |
| 232 | reg = free_reg; |
| 233 | } |
| 234 | |
| 235 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 236 | return resource; |
| 237 | } |
| 238 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 239 | static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 240 | { |
| 241 | struct resource *resource; |
| 242 | |
| 243 | /* Initialize the io space constraints on the current bus */ |
| 244 | resource = amdfam16_find_iopair(dev, nodeid, link); |
| 245 | if (resource) { |
| 246 | u32 align; |
| 247 | align = log2(HT_IO_HOST_ALIGN); |
| 248 | resource->base = 0; |
| 249 | resource->size = 0; |
| 250 | resource->align = align; |
| 251 | resource->gran = align; |
| 252 | resource->limit = 0xffffUL; |
| 253 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 254 | } |
| 255 | |
| 256 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 257 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 258 | if (resource) { |
| 259 | resource->base = 0; |
| 260 | resource->size = 0; |
| 261 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 262 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 263 | resource->limit = 0xffffffffffULL; |
| 264 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 265 | resource->flags |= IORESOURCE_BRIDGE; |
| 266 | } |
| 267 | |
| 268 | /* Initialize the memory constraints on the current bus */ |
| 269 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 270 | if (resource) { |
| 271 | resource->base = 0; |
| 272 | resource->size = 0; |
| 273 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 274 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 275 | resource->limit = 0xffffffffffULL; |
| 276 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 277 | } |
| 278 | |
| 279 | } |
| 280 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 281 | static void read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 282 | { |
| 283 | u32 nodeid; |
| 284 | struct bus *link; |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 285 | struct resource *res; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 286 | |
| 287 | nodeid = amdfam16_nodeid(dev); |
| 288 | for (link = dev->link_list; link; link = link->next) { |
| 289 | if (link->children) { |
| 290 | amdfam16_link_read_bases(dev, nodeid, link->link_num); |
| 291 | } |
| 292 | } |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 293 | |
| 294 | /* |
| 295 | * This MMCONF resource must be reserved in the PCI domain. |
| 296 | * It is not honored by the coreboot resource allocator if it is in |
| 297 | * the CPU_CLUSTER. |
| 298 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 299 | mmconf_resource(dev, MMIO_CONF_BASE); |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 300 | |
| 301 | /* NB IOAPIC2 resource */ |
| 302 | res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ |
| 303 | res->base = IO_APIC2_ADDR; |
| 304 | res->size = 0x00001000; |
| 305 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 306 | } |
| 307 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 308 | static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 309 | { |
| 310 | resource_t rbase, rend; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 311 | unsigned int reg, link_num; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 312 | char buf[50]; |
| 313 | |
| 314 | /* Make certain the resource has actually been set */ |
| 315 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 316 | return; |
| 317 | } |
| 318 | |
| 319 | /* If I have already stored this resource don't worry about it */ |
| 320 | if (resource->flags & IORESOURCE_STORED) { |
| 321 | return; |
| 322 | } |
| 323 | |
| 324 | /* Only handle PCI memory and IO resources */ |
| 325 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 326 | return; |
| 327 | |
| 328 | /* Ensure I am actually looking at a resource of function 1 */ |
| 329 | if ((resource->index & 0xffff) < 0x1000) { |
| 330 | return; |
| 331 | } |
| 332 | /* Get the base address */ |
| 333 | rbase = resource->base; |
| 334 | |
| 335 | /* Get the limit (rounded up) */ |
| 336 | rend = resource_end(resource); |
| 337 | |
| 338 | /* Get the register and link */ |
| 339 | reg = resource->index & 0xfff; // 4k |
| 340 | link_num = IOINDEX_LINK(resource->index); |
| 341 | |
| 342 | if (resource->flags & IORESOURCE_IO) { |
| 343 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 344 | } |
| 345 | else if (resource->flags & IORESOURCE_MEM) { |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 346 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 347 | } |
| 348 | resource->flags |= IORESOURCE_STORED; |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 349 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 350 | nodeid, link_num); |
| 351 | report_resource_stored(dev, resource, buf); |
| 352 | } |
| 353 | |
| 354 | /** |
| 355 | * I tried to reuse the resource allocation code in set_resource() |
| 356 | * but it is too difficult to deal with the resource allocation magic. |
| 357 | */ |
| 358 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 359 | static void create_vga_resource(struct device *dev, unsigned int nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 360 | { |
| 361 | struct bus *link; |
| 362 | |
| 363 | /* find out which link the VGA card is connected, |
| 364 | * we only deal with the 'first' vga card */ |
| 365 | for (link = dev->link_list; link; link = link->next) { |
| 366 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 367 | #if CONFIG(MULTIPLE_VGA_ADAPTERS) |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 368 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 369 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 370 | link->secondary,link->subordinate); |
| 371 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 372 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 373 | (vga_pri->bus->secondary <= link->subordinate)) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 374 | #endif |
| 375 | break; |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | /* no VGA card installed */ |
| 380 | if (link == NULL) |
| 381 | return; |
| 382 | |
| 383 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 384 | set_vga_enable_reg(nodeid, sblink); |
| 385 | } |
| 386 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 387 | static void set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 388 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 389 | unsigned int nodeid; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 390 | struct bus *bus; |
| 391 | struct resource *res; |
| 392 | |
| 393 | /* Find the nodeid */ |
| 394 | nodeid = amdfam16_nodeid(dev); |
| 395 | |
| 396 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 397 | |
| 398 | /* Set each resource we have found */ |
| 399 | for (res = dev->resource_list; res; res = res->next) { |
| 400 | set_resource(dev, res, nodeid); |
| 401 | } |
| 402 | |
| 403 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 404 | if (bus->children) { |
| 405 | assign_resources(bus); |
| 406 | } |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | static void northbridge_init(struct device *dev) |
| 411 | { |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 412 | setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 413 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 414 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 415 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 416 | { |
| 417 | void *addr, *current; |
| 418 | |
| 419 | /* Skip the HEST header. */ |
| 420 | current = (void *)(hest + 1); |
| 421 | |
| 422 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 423 | if (addr != NULL) |
| 424 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 425 | |
| 426 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 427 | if (addr != NULL) |
| 428 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 429 | |
| 430 | return (unsigned long)current; |
| 431 | } |
| 432 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 433 | unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 434 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 435 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 436 | current = ALIGN_UP(current, 8); |
| 437 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 438 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 439 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 440 | ivhd_ioapic->reserved = 0x0000; |
| 441 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 442 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 443 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
| 444 | ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ |
| 445 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 446 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 447 | current += sizeof(ivrs_ivhd_special_t); |
| 448 | |
| 449 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
| 450 | |
| 451 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 452 | ivhd_ioapic->reserved = 0x0000; |
| 453 | ivhd_ioapic->dte_setting = 0x00; |
| 454 | ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ |
| 455 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 456 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 457 | current += sizeof(ivrs_ivhd_special_t); |
| 458 | |
| 459 | return current; |
| 460 | } |
| 461 | |
| 462 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 463 | { |
| 464 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 465 | current = ALIGN_UP(current, 8); |
| 466 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 467 | |
| 468 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 469 | ivhd_hpet->reserved = 0x0000; |
| 470 | ivhd_hpet->dte_setting = 0x00; |
| 471 | ivhd_hpet->handle = 0x00; |
| 472 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 473 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 474 | current += sizeof(ivrs_ivhd_special_t); |
| 475 | |
| 476 | return current; |
| 477 | } |
| 478 | |
| 479 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 480 | uint16_t end_devid, uint8_t setting) |
| 481 | { |
| 482 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 483 | current = ALIGN_UP(current, 4); |
| 484 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 485 | |
| 486 | /* Create the start range IVHD entry */ |
| 487 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 488 | ivhd_range->dev_id = start_devid; |
| 489 | ivhd_range->dte_setting = setting; |
| 490 | current += sizeof(ivrs_ivhd_generic_t); |
| 491 | |
| 492 | /* Create the end range IVHD entry */ |
| 493 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 494 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 495 | ivhd_range->dev_id = end_devid; |
| 496 | ivhd_range->dte_setting = setting; |
| 497 | current += sizeof(ivrs_ivhd_generic_t); |
| 498 | |
| 499 | return current; |
| 500 | } |
| 501 | |
| 502 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 503 | unsigned long *current, uint8_t type, uint8_t data) |
| 504 | { |
| 505 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 506 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 507 | *current = ALIGN_UP(*current, 4); |
| 508 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 509 | |
| 510 | ivhd_entry->type = type; |
| 511 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 512 | ivhd_entry->dte_setting = data; |
| 513 | *current += sizeof(ivrs_ivhd_generic_t); |
| 514 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 515 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 516 | *current = ALIGN_UP(*current, 8); |
| 517 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 518 | |
| 519 | ivhd_entry->type = type; |
| 520 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 521 | ivhd_entry->dte_setting = data; |
| 522 | ivhd_entry->reserved1 = 0; |
| 523 | ivhd_entry->reserved2 = 0; |
| 524 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 525 | (parent->bus->secondary << 8); |
| 526 | *current += sizeof(ivrs_ivhd_alias_t); |
| 527 | } |
| 528 | |
| 529 | return *current; |
| 530 | } |
| 531 | |
| 532 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 533 | unsigned long *current, uint16_t *ivhd_length) |
| 534 | { |
| 535 | unsigned int header_type, is_pcie; |
| 536 | unsigned long current_backup; |
| 537 | |
| 538 | header_type = dev->hdr_type & 0x7f; |
| 539 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 540 | |
| 541 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 542 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 543 | /* Device or Bridge is PCIe */ |
| 544 | current_backup = *current; |
| 545 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 546 | *ivhd_length += (*current - current_backup); |
| 547 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 548 | /* Device is legacy PCI or PCI-X */ |
| 549 | current_backup = *current; |
| 550 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 551 | *ivhd_length += (*current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 552 | } |
| 553 | } |
| 554 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 555 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 556 | unsigned int depth, int linknum, int8_t *root_level, |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 557 | unsigned long *current, uint16_t *ivhd_length) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 558 | { |
| 559 | struct device *sibling; |
| 560 | struct bus *link; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 561 | |
| 562 | if (!root_level) { |
| 563 | root_level = malloc(sizeof(int8_t)); |
| 564 | *root_level = -1; |
| 565 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 566 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 567 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 568 | |
| 569 | if ((dev->bus->secondary == 0x0) && |
| 570 | (dev->path.pci.devfn == 0x0)) |
| 571 | *root_level = depth; |
| 572 | |
| 573 | if ((*root_level != -1) && (dev->enabled)) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 574 | if (depth != *root_level) |
| 575 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 576 | } |
| 577 | } |
| 578 | |
| 579 | for (link = dev->link_list; link; link = link->next) |
| 580 | for (sibling = link->children; sibling; sibling = |
| 581 | sibling->sibling) |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 582 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 583 | current, ivhd_length); |
| 584 | |
| 585 | free(root_level); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 586 | } |
| 587 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 588 | #define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) |
| 589 | #define EFR_SUPPORT BIT(27) |
| 590 | |
| 591 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 592 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 593 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 594 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 595 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 596 | /* |
| 597 | * These devices should be already found by previous function. |
| 598 | * Do not perform NULL checks. |
| 599 | */ |
| 600 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 601 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 602 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 603 | /* |
| 604 | * In order to utilize all features, firmware should expose type 11h |
| 605 | * IVHD which supersedes the type 10h. |
| 606 | */ |
| 607 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 608 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 609 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 610 | /* Enable EFR */ |
| 611 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 612 | /* For type 11h bits 6 and 7 are reserved */ |
| 613 | ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; |
| 614 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 615 | /* BDF <bus>:00.2 */ |
| 616 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 617 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
| 618 | ivhd_11->capability_offset = 0x40; |
| 619 | ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 620 | ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 621 | ivhd_11->pci_segment_group = 0x0000; |
| 622 | ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 623 | ivhd_11->iommu_attributes.perf_counters = |
| 624 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; |
| 625 | ivhd_11->iommu_attributes.perf_counter_banks = |
| 626 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; |
| 627 | ivhd_11->iommu_attributes.msi_num_ppr = |
| 628 | (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 629 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 630 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { |
| 631 | ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); |
| 632 | ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); |
| 633 | } |
| 634 | |
| 635 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 636 | |
| 637 | /* Now repeat all the device entries from type 10h */ |
| 638 | current_backup = current; |
| 639 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 640 | ivhd_11->length += (current - current_backup); |
| 641 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); |
| 642 | |
| 643 | /* Describe HPET */ |
| 644 | current_backup = current; |
| 645 | current = ivhd_describe_hpet(current); |
| 646 | ivhd_11->length += (current - current_backup); |
| 647 | |
| 648 | /* Describe IOAPICs */ |
| 649 | current_backup = current; |
| 650 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 651 | ivhd_11->length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 652 | |
| 653 | return current; |
| 654 | } |
| 655 | |
| 656 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 657 | { |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 658 | acpi_ivrs_t *ivrs_agesa; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 659 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 660 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 661 | struct device *nb_dev = pcidev_on_root(0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 662 | if (!nb_dev) { |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 663 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 664 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 665 | |
| 666 | return (unsigned long)ivrs; |
| 667 | } |
| 668 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 669 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 670 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 671 | if (!iommu_dev) { |
| 672 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 673 | |
| 674 | return (unsigned long)ivrs; |
| 675 | } |
| 676 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 677 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 678 | if (ivrs_agesa != NULL) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 679 | ivrs->iv_info = ivrs_agesa->iv_info; |
| 680 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 681 | ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 682 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 683 | /* BDF <bus>:00.2 */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 684 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 685 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 686 | ivrs->ivhd.capability_offset = 0x40; |
| 687 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 688 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 689 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 690 | ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 691 | ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; |
| 692 | /* Enable EFR if supported */ |
| 693 | if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) |
| 694 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 695 | } else { |
| 696 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 697 | |
| 698 | return (unsigned long)ivrs; |
| 699 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 700 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 701 | /* |
| 702 | * Add all possible PCI devices on bus 0 that can generate transactions |
| 703 | * processed by IOMMU. Start with device 00:01.0 since IOMMU does not |
| 704 | * translate transactions generated by itself. |
| 705 | */ |
| 706 | current_backup = current; |
| 707 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 708 | ivrs->ivhd.length += (current - current_backup); |
| 709 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 710 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 711 | /* Describe HPET */ |
| 712 | current_backup = current; |
| 713 | current = ivhd_describe_hpet(current); |
| 714 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 715 | |
| 716 | /* Describe IOAPICs */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 717 | current_backup = current; |
| 718 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 719 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 720 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 721 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 722 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 723 | return current; |
| 724 | |
| 725 | return acpi_fill_ivrs11(current, ivrs_agesa); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 726 | } |
| 727 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 728 | static void northbridge_fill_ssdt_generator(const struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 729 | { |
| 730 | msr_t msr; |
| 731 | char pscope[] = "\\_SB.PCI0"; |
| 732 | |
| 733 | acpigen_write_scope(pscope); |
| 734 | msr = rdmsr(TOP_MEM); |
| 735 | acpigen_write_name_dword("TOM1", msr.lo); |
| 736 | msr = rdmsr(TOP_MEM2); |
| 737 | /* |
| 738 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 739 | * here. |
| 740 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 741 | * slide 22ff. |
| 742 | * Shift value right by 20 bit to make it fit into 32bit, |
| 743 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 744 | */ |
| 745 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 746 | acpigen_pop_len(); |
| 747 | } |
| 748 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 749 | static void patch_ssdt_processor_scope(acpi_header_t *ssdt) |
| 750 | { |
| 751 | unsigned int len = ssdt->length - sizeof(acpi_header_t); |
| 752 | unsigned int i; |
| 753 | |
| 754 | for (i = sizeof(acpi_header_t); i < len; i++) { |
| 755 | /* Search for _PR_ scope and replace it with _SB_ */ |
| 756 | if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) |
| 757 | *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; |
| 758 | } |
| 759 | /* Recalculate checksum */ |
| 760 | ssdt->checksum = 0; |
| 761 | ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); |
| 762 | } |
| 763 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 764 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 765 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 766 | acpi_rsdp_t *rsdp) |
| 767 | { |
| 768 | acpi_srat_t *srat; |
| 769 | acpi_slit_t *slit; |
| 770 | acpi_header_t *ssdt; |
| 771 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 772 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 773 | |
| 774 | /* HEST */ |
| 775 | current = ALIGN(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 776 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 777 | acpi_add_table(rsdp, (void *)current); |
| 778 | current += ((acpi_header_t *)current)->length; |
| 779 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 780 | /* IVRS */ |
| 781 | current = ALIGN(current, 8); |
| 782 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 783 | ivrs = (acpi_ivrs_t *) current; |
| 784 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 785 | current += ivrs->header.length; |
| 786 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 787 | |
| 788 | /* SRAT */ |
| 789 | current = ALIGN(current, 8); |
| 790 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 791 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 792 | if (srat != NULL) { |
| 793 | memcpy((void *)current, srat, srat->header.length); |
| 794 | srat = (acpi_srat_t *) current; |
| 795 | current += srat->header.length; |
| 796 | acpi_add_table(rsdp, srat); |
| 797 | } else { |
| 798 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 799 | } |
| 800 | |
| 801 | /* SLIT */ |
| 802 | current = ALIGN(current, 8); |
| 803 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 804 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 805 | if (slit != NULL) { |
| 806 | memcpy((void *)current, slit, slit->header.length); |
| 807 | slit = (acpi_slit_t *) current; |
| 808 | current += slit->header.length; |
| 809 | acpi_add_table(rsdp, slit); |
| 810 | } else { |
| 811 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 812 | } |
| 813 | |
| 814 | /* ALIB */ |
| 815 | current = ALIGN(current, 16); |
| 816 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 817 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 818 | if (alib != NULL) { |
| 819 | memcpy((void *)current, alib, alib->length); |
| 820 | alib = (acpi_header_t *) current; |
| 821 | current += alib->length; |
| 822 | acpi_add_table(rsdp, (void *)alib); |
| 823 | } |
| 824 | else { |
| 825 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 826 | } |
| 827 | |
| 828 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 829 | /* SSDT */ |
| 830 | current = ALIGN(current, 16); |
| 831 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 832 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 833 | if (ssdt != NULL) { |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 834 | patch_ssdt_processor_scope(ssdt); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 835 | memcpy((void *)current, ssdt, ssdt->length); |
| 836 | ssdt = (acpi_header_t *) current; |
| 837 | current += ssdt->length; |
| 838 | } |
| 839 | else { |
| 840 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 841 | } |
| 842 | acpi_add_table(rsdp,ssdt); |
| 843 | |
| 844 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 845 | return current; |
| 846 | } |
| 847 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 848 | static struct device_operations northbridge_operations = { |
| 849 | .read_resources = read_resources, |
| 850 | .set_resources = set_resources, |
| 851 | .enable_resources = pci_dev_enable_resources, |
| 852 | .init = northbridge_init, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 853 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 854 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 855 | }; |
| 856 | |
| 857 | static const struct pci_driver family16_northbridge __pci_driver = { |
| 858 | .ops = &northbridge_operations, |
| 859 | .vendor = PCI_VENDOR_ID_AMD, |
Marshall Dawson | 463f46e | 2016-10-14 20:46:08 -0600 | [diff] [blame] | 860 | .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 861 | }; |
| 862 | |
| 863 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 864 | .ops = &northbridge_operations, |
| 865 | .vendor = PCI_VENDOR_ID_AMD, |
| 866 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 867 | }; |
| 868 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 869 | static void fam16_finalize(void *chip_info) |
| 870 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 871 | struct device *dev; |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 872 | u32 value; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 873 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 874 | pci_write_config32(dev, 0xF8, 0); |
| 875 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 876 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 877 | /* |
| 878 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 879 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 880 | * right function that enables these functionalities. Disabled ACS |
| 881 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 882 | * group. Without IOMMU group separation the devices cannot be passed |
| 883 | * through independently. |
| 884 | */ |
| 885 | |
| 886 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 887 | pci_write_config32(dev, 0xE0, 0x014000B0); |
| 888 | value = pci_read_config32(dev, 0xE4); |
| 889 | |
| 890 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
| 891 | value |= PCIE_CAP_AER | PCIE_CAP_ACS; |
| 892 | pci_write_config32(dev, 0xE4, value); |
| 893 | |
| 894 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 895 | pci_write_config32(dev, 0xE0, 0x01300000); |
| 896 | value = pci_read_config32(dev, 0xE4); |
| 897 | |
| 898 | /* |
| 899 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 900 | * looks like these bits enable: Source Validation and Translation |
| 901 | * Blocking |
| 902 | */ |
| 903 | value |= (BIT(24) | BIT(25) | BIT(26)); |
| 904 | pci_write_config32(dev, 0xE4, value); |
| 905 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 906 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 907 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 908 | if (dev != NULL) { |
| 909 | value = pci_read_config32(dev, 0x60); |
| 910 | value &= ~(1 << 11); |
| 911 | pci_write_config32(dev, 0x60, value); |
| 912 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 913 | } |
| 914 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 915 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 916 | CHIP_NAME("AMD FAM16 Northbridge") |
| 917 | .enable_dev = 0, |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 918 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 919 | }; |
| 920 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 921 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 922 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 923 | unsigned int reg; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 924 | |
| 925 | /* Find the already assigned resource pairs */ |
| 926 | get_fx_devs(); |
| 927 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 928 | u32 base, limit; |
| 929 | base = f1_read_config32(reg); |
| 930 | limit = f1_read_config32(reg + 0x04); |
| 931 | /* Is this register allocated? */ |
| 932 | if ((base & 3) != 0) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 933 | unsigned int nodeid, reg_link; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 934 | struct device *reg_dev; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 935 | if (reg < 0xc0) { // mmio |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 936 | nodeid = (limit & 0xf) + (base&0x30); |
| 937 | } else { // io |
| 938 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 939 | } |
| 940 | reg_link = (limit >> 4) & 7; |
| 941 | reg_dev = __f0_dev[nodeid]; |
| 942 | if (reg_dev) { |
| 943 | /* Reserve the resource */ |
| 944 | struct resource *res; |
| 945 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 946 | if (res) { |
| 947 | res->flags = 1; |
| 948 | } |
| 949 | } |
| 950 | } |
| 951 | } |
| 952 | /* FIXME: do we need to check extend conf space? |
| 953 | I don't believe that much preset value */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 954 | pci_domain_read_resources(dev); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 955 | } |
| 956 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 957 | static void domain_enable_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 958 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 959 | } |
| 960 | |
| 961 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 962 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 963 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 964 | int node_id; |
| 965 | }; |
| 966 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 967 | { |
| 968 | struct hw_mem_hole_info mem_hole; |
| 969 | int i; |
| 970 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 971 | mem_hole.node_id = -1; |
| 972 | for (i = 0; i < node_nums; i++) { |
| 973 | dram_base_mask_t d; |
| 974 | u32 hole; |
| 975 | d = get_dram_base_mask(i); |
| 976 | if (!(d.mask & 1)) continue; // no memory on this node |
| 977 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 978 | if (hole & 2) { // we find the hole |
| 979 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 980 | mem_hole.node_id = i; // record the node No with hole |
| 981 | break; // only one hole |
| 982 | } |
| 983 | } |
| 984 | |
| 985 | /* We need to double check if there is special set on base reg and limit reg |
| 986 | * are not continuous instead of hole, it will find out its hole_startk. |
| 987 | */ |
| 988 | if (mem_hole.node_id == -1) { |
| 989 | resource_t limitk_pri = 0; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 990 | for (i = 0; i < node_nums; i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 991 | dram_base_mask_t d; |
| 992 | resource_t base_k, limit_k; |
| 993 | d = get_dram_base_mask(i); |
| 994 | if (!(d.base & 1)) continue; |
| 995 | base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; |
| 996 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 997 | if (limitk_pri != base_k) { // we find the hole |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 998 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 999 | mem_hole.node_id = i; |
| 1000 | break; //only one hole |
| 1001 | } |
| 1002 | limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
| 1003 | limitk_pri = limit_k; |
| 1004 | } |
| 1005 | } |
| 1006 | return mem_hole; |
| 1007 | } |
| 1008 | #endif |
| 1009 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1010 | static void domain_set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1011 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1012 | unsigned long mmio_basek; |
| 1013 | u32 pci_tolm; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1014 | int i, idx; |
| 1015 | struct bus *link; |
| 1016 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 1017 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1018 | #endif |
| 1019 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1020 | pci_tolm = 0xffffffffUL; |
| 1021 | for (link = dev->link_list; link; link = link->next) { |
| 1022 | pci_tolm = find_pci_tolm(link); |
| 1023 | } |
| 1024 | |
| 1025 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 1026 | // amdk8, too. |
| 1027 | mmio_basek = pci_tolm >> 10; |
| 1028 | /* Round mmio_basek to something the processor can support */ |
| 1029 | mmio_basek &= ~((1 << 6) -1); |
| 1030 | |
| 1031 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 1032 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 1033 | /* Round the mmio hole to 64M */ |
| 1034 | mmio_basek &= ~((64*1024) - 1); |
| 1035 | |
| 1036 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 1037 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 1038 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 1039 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 1040 | * otherwise We reset the hole to the mmio_basek |
| 1041 | */ |
| 1042 | |
| 1043 | mem_hole = get_hw_mem_hole_info(); |
| 1044 | |
| 1045 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 1046 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 1047 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1048 | } |
| 1049 | #endif |
| 1050 | |
| 1051 | idx = 0x10; |
| 1052 | for (i = 0; i < node_nums; i++) { |
| 1053 | dram_base_mask_t d; |
| 1054 | resource_t basek, limitk, sizek; // 4 1T |
| 1055 | |
| 1056 | d = get_dram_base_mask(i); |
| 1057 | |
| 1058 | if (!(d.mask & 1)) continue; |
| 1059 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 1060 | limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1061 | |
| 1062 | sizek = limitk - basek; |
| 1063 | |
| 1064 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 1065 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 1066 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 1067 | idx += 0x10; |
| 1068 | basek = (8*64)+(16*16); |
| 1069 | sizek = limitk - ((8*64)+(16*16)); |
| 1070 | |
| 1071 | } |
| 1072 | |
| 1073 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 1074 | |
| 1075 | /* split the region to accommodate pci memory space */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1076 | if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1077 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1078 | unsigned int pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1079 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1080 | if (pre_sizek > 0) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1081 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 1082 | idx += 0x10; |
| 1083 | sizek -= pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1084 | } |
| 1085 | basek = mmio_basek; |
| 1086 | } |
| 1087 | if ((basek + sizek) <= 4*1024*1024) { |
| 1088 | sizek = 0; |
| 1089 | } |
| 1090 | else { |
| 1091 | uint64_t topmem2 = bsp_topmem2(); |
| 1092 | basek = 4*1024*1024; |
| 1093 | sizek = topmem2/1024 - basek; |
| 1094 | } |
| 1095 | } |
| 1096 | |
| 1097 | ram_resource(dev, (idx | i), basek, sizek); |
| 1098 | idx += 0x10; |
| 1099 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 1100 | i, mmio_basek, basek, limitk); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1101 | } |
| 1102 | |
Kyösti Mälkki | e87564f | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 1103 | add_uma_resource_below_tolm(dev, 7); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1104 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1105 | for (link = dev->link_list; link; link = link->next) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1106 | if (link->children) { |
| 1107 | assign_resources(link); |
| 1108 | } |
| 1109 | } |
| 1110 | } |
| 1111 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 1112 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1113 | { |
| 1114 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 1115 | return "PCI0"; |
| 1116 | |
| 1117 | return NULL; |
| 1118 | } |
| 1119 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1120 | static struct device_operations pci_domain_ops = { |
| 1121 | .read_resources = domain_read_resources, |
| 1122 | .set_resources = domain_set_resources, |
| 1123 | .enable_resources = domain_enable_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1124 | .scan_bus = pci_domain_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1125 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1126 | }; |
| 1127 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1128 | static void sysconf_init(struct device *dev) // first node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1129 | { |
| 1130 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 1131 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 1132 | } |
| 1133 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1134 | static void cpu_bus_scan(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1135 | { |
| 1136 | struct bus *cpu_bus; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1137 | struct device *dev_mc; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1138 | int i,j; |
| 1139 | int coreid_bits; |
| 1140 | int core_max = 0; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1141 | unsigned int ApicIdCoreIdSize; |
| 1142 | unsigned int core_nums; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1143 | int siblings = 0; |
| 1144 | unsigned int family; |
| 1145 | u32 modules = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1146 | int ioapic_count = 0; |
| 1147 | |
Michał Żygowski | e719288 | 2019-11-23 19:02:19 +0100 | [diff] [blame] | 1148 | /* For binaryPI there is no multiprocessor configuration, the number of |
| 1149 | * modules will always be 1. */ |
| 1150 | modules = 1; |
| 1151 | ioapic_count = CONFIG_NUM_OF_IOAPICS; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1152 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1153 | dev_mc = pcidev_on_root(DEV_CDB, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1154 | if (!dev_mc) { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1155 | printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1156 | die(""); |
| 1157 | } |
| 1158 | sysconf_init(dev_mc); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1159 | |
| 1160 | /* Get Max Number of cores(MNC) */ |
Kyösti Mälkki | d41feed | 2017-09-24 16:23:57 +0300 | [diff] [blame] | 1161 | coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1162 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 1163 | |
| 1164 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 1165 | if (ApicIdCoreIdSize) { |
| 1166 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 1167 | } else { |
| 1168 | core_nums = 3; //quad core |
| 1169 | } |
| 1170 | |
| 1171 | /* Find which cpus are present */ |
| 1172 | cpu_bus = dev->link_list; |
| 1173 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1174 | struct device *cdb_dev; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1175 | unsigned int devn; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1176 | struct bus *pbus; |
| 1177 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1178 | devn = DEV_CDB + i; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1179 | pbus = dev_mc->bus; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1180 | |
| 1181 | /* Find the cpu's pci device */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1182 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1183 | if (!cdb_dev) { |
| 1184 | /* If I am probing things in a weird order |
| 1185 | * ensure all of the cpu's pci devices are found. |
| 1186 | */ |
| 1187 | int fn; |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1188 | for (fn = 0; fn <= 5; fn++) { //FBDIMM? |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1189 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 1190 | PCI_DEVFN(devn, fn)); |
| 1191 | } |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1192 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1193 | } else { |
| 1194 | /* Ok, We need to set the links for that device. |
| 1195 | * otherwise the device under it will not be scanned |
| 1196 | */ |
Kyösti Mälkki | c5163ed8 | 2015-02-04 13:25:37 +0200 | [diff] [blame] | 1197 | |
| 1198 | add_more_links(cdb_dev, 4); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | family = cpuid_eax(1); |
| 1202 | family = (family >> 20) & 0xFF; |
| 1203 | if (family == 1) { //f10 |
| 1204 | u32 dword; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1205 | cdb_dev = pcidev_on_root(devn, 3); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1206 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 1207 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 1208 | } else if (family == 7) {//f16 |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1209 | cdb_dev = pcidev_on_root(devn, 5); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1210 | if (cdb_dev && cdb_dev->enabled) { |
| 1211 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 1212 | siblings &= 0xFF; |
| 1213 | } |
| 1214 | } else { |
| 1215 | siblings = 0; //default one core |
| 1216 | } |
| 1217 | int enable_node = cdb_dev && cdb_dev->enabled; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1218 | printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1219 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 1220 | |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1221 | for (j = 0; j <= siblings; j++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1222 | u32 lapicid_start = 0; |
| 1223 | |
| 1224 | /* |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 1225 | * APIC ID calculation is tightly coupled with AGESA v5 code. |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1226 | * This calculation MUST match the assignment calculation done |
| 1227 | * in LocalApicInitializationAtEarly() function. |
| 1228 | * And reference GetLocalApicIdForCore() |
| 1229 | * |
Elyes HAOUAS | a5b0bc4 | 2020-02-20 20:04:29 +0100 | [diff] [blame] | 1230 | * Apply APIC enumeration rules |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1231 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 1232 | * put the local-APICs at m..z |
| 1233 | * |
| 1234 | * This is needed because many IO-APIC devices only have 4 bits |
| 1235 | * for their APIC id and therefore must reside at 0..15 |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 1236 | */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1237 | if ((node_nums * core_max) + ioapic_count >= 0x10) { |
| 1238 | lapicid_start = (ioapic_count - 1) / core_max; |
| 1239 | lapicid_start = (lapicid_start + 1) * core_max; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1240 | printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1241 | } |
| 1242 | u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1243 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1244 | i, j, apic_id); |
| 1245 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1246 | struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1247 | if (cpu) |
| 1248 | amd_cpu_topology(cpu, i, j); |
| 1249 | } //j |
| 1250 | } |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1251 | } |
| 1252 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1253 | static void cpu_bus_init(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1254 | { |
| 1255 | initialize_cpus(dev->link_list); |
| 1256 | } |
| 1257 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1258 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 1259 | .read_resources = noop_read_resources, |
| 1260 | .set_resources = noop_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1261 | .init = cpu_bus_init, |
| 1262 | .scan_bus = cpu_bus_scan, |
| 1263 | }; |
| 1264 | |
| 1265 | static void root_complex_enable_dev(struct device *dev) |
| 1266 | { |
| 1267 | static int done = 0; |
| 1268 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1269 | if (!done) { |
| 1270 | setup_bsp_ramtop(); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1271 | done = 1; |
| 1272 | } |
| 1273 | |
| 1274 | /* Set the operations if it is a special bus type */ |
| 1275 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 1276 | dev->ops = &pci_domain_ops; |
| 1277 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 1278 | dev->ops = &cpu_bus_ops; |
| 1279 | } |
| 1280 | } |
| 1281 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1282 | struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1283 | CHIP_NAME("AMD FAM16 Root Complex") |
| 1284 | .enable_dev = root_complex_enable_dev, |
| 1285 | }; |
| 1286 | |
| 1287 | /********************************************************************* |
| 1288 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 1289 | *********************************************************************/ |
| 1290 | u32 map_oprom_vendev(u32 vendev) |
| 1291 | { |
| 1292 | u32 new_vendev; |
| 1293 | new_vendev = |
| 1294 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 1295 | |
| 1296 | if (vendev != new_vendev) |
| 1297 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 1298 | |
| 1299 | return new_vendev; |
| 1300 | } |