Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 16 | #include <device/pci_ops.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 17 | #include <arch/acpi.h> |
| 18 | #include <stdint.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <device/hypertransport.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 23 | #include <string.h> |
| 24 | #include <lib.h> |
| 25 | #include <cpu/cpu.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 26 | #include <Porting.h> |
| 27 | #include <AGESA.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 28 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <cpu/amd/msr.h> |
| 31 | #include <cpu/amd/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 32 | #include <arch/acpigen.h> |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 33 | #include <northbridge/amd/pi/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 34 | #include <northbridge/amd/agesa/agesa_helper.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 35 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 36 | #define MAX_NODE_NUMS MAX_NODES |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 37 | #define PCIE_CAP_AER BIT(5) |
| 38 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 39 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 40 | typedef struct dram_base_mask { |
| 41 | u32 base; //[47:27] at [28:8] |
| 42 | u32 mask; //[47:27] at [28:8] and enable at bit 0 |
| 43 | } dram_base_mask_t; |
| 44 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 45 | static unsigned int node_nums; |
| 46 | static unsigned int sblink; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 47 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 48 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 49 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 50 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 51 | static unsigned int fx_devs = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 52 | |
| 53 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 54 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 55 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 56 | dram_base_mask_t d; |
| 57 | dev = __f1_dev[0]; |
| 58 | u32 temp; |
| 59 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 60 | d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too |
| 61 | temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 62 | d.mask |= temp<<21; |
| 63 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 64 | d.mask |= (temp & 1); // enable bit |
| 65 | d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too |
| 66 | temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 67 | d.base |= temp<<21; |
| 68 | return d; |
| 69 | } |
| 70 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 71 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 72 | u32 io_min, u32 io_max) |
| 73 | { |
| 74 | u32 i; |
| 75 | u32 tempreg; |
| 76 | /* io range allocation */ |
| 77 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 78 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 79 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 80 | tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 81 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 82 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 83 | } |
| 84 | |
| 85 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 86 | { |
| 87 | u32 i; |
| 88 | u32 tempreg; |
| 89 | /* io range allocation */ |
| 90 | tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 91 | for (i = 0; i < nodes; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 92 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 93 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 94 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 95 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 96 | } |
| 97 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 98 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 99 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 100 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | static void get_fx_devs(void) |
| 104 | { |
| 105 | int i; |
| 106 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 107 | __f0_dev[i] = get_node_pci(i, 0); |
| 108 | __f1_dev[i] = get_node_pci(i, 1); |
| 109 | __f2_dev[i] = get_node_pci(i, 2); |
| 110 | __f4_dev[i] = get_node_pci(i, 4); |
| 111 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 112 | fx_devs = i+1; |
| 113 | } |
| 114 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 115 | die("Cannot find 0:0x18.[0|1]\n"); |
| 116 | } |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 117 | printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 118 | } |
| 119 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 120 | static u32 f1_read_config32(unsigned int reg) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 121 | { |
| 122 | if (fx_devs == 0) |
| 123 | get_fx_devs(); |
| 124 | return pci_read_config32(__f1_dev[0], reg); |
| 125 | } |
| 126 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 127 | static void f1_write_config32(unsigned int reg, u32 value) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 128 | { |
| 129 | int i; |
| 130 | if (fx_devs == 0) |
| 131 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 132 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 133 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 134 | dev = __f1_dev[i]; |
| 135 | if (dev && dev->enabled) { |
| 136 | pci_write_config32(dev, reg, value); |
| 137 | } |
| 138 | } |
| 139 | } |
| 140 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 141 | static u32 amdfam16_nodeid(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 142 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 143 | return (dev->path.pci.devfn >> 3) - DEV_CDB; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 147 | { |
| 148 | u32 val; |
| 149 | |
| 150 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 151 | /* it will routing |
| 152 | * (1)mmio 0xa0000:0xbffff |
| 153 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 154 | */ |
| 155 | f1_write_config32(0xf4, val); |
| 156 | |
| 157 | } |
| 158 | |
| 159 | /** |
| 160 | * @return |
Elyes HAOUAS | 99b075a | 2019-12-30 14:29:31 +0100 | [diff] [blame] | 161 | * @retval 2 resource does not exist, usable |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 162 | * @retval 0 resource exists, not usable |
| 163 | * @retval 1 resource exist, resource has been allocated before |
| 164 | */ |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 165 | static int reg_useable(unsigned int reg, struct device *goal_dev, |
| 166 | unsigned int goal_nodeid, unsigned int goal_link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 167 | { |
| 168 | struct resource *res; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 169 | unsigned int nodeid, link = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 170 | int result; |
| 171 | res = 0; |
| 172 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 173 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 174 | dev = __f0_dev[nodeid]; |
| 175 | if (!dev) |
| 176 | continue; |
| 177 | for (link = 0; !res && (link < 8); link++) { |
| 178 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 179 | } |
| 180 | } |
| 181 | result = 2; |
| 182 | if (res) { |
| 183 | result = 0; |
| 184 | if ((goal_link == (link - 1)) && |
| 185 | (goal_nodeid == (nodeid - 1)) && |
| 186 | (res->flags <= 1)) { |
| 187 | result = 1; |
| 188 | } |
| 189 | } |
| 190 | return result; |
| 191 | } |
| 192 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 193 | static struct resource *amdfam16_find_iopair(struct device *dev, |
| 194 | unsigned int nodeid, unsigned int link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 195 | { |
| 196 | struct resource *resource; |
| 197 | u32 free_reg, reg; |
| 198 | resource = 0; |
| 199 | free_reg = 0; |
| 200 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 201 | int result; |
| 202 | result = reg_useable(reg, dev, nodeid, link); |
| 203 | if (result == 1) { |
| 204 | /* I have been allocated this one */ |
| 205 | break; |
| 206 | } |
| 207 | else if (result > 1) { |
| 208 | /* I have a free register pair */ |
| 209 | free_reg = reg; |
| 210 | } |
| 211 | } |
| 212 | if (reg > 0xd8) { |
| 213 | reg = free_reg; // if no free, the free_reg still be 0 |
| 214 | } |
| 215 | |
| 216 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 217 | |
| 218 | return resource; |
| 219 | } |
| 220 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 221 | static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 222 | { |
| 223 | struct resource *resource; |
| 224 | u32 free_reg, reg; |
| 225 | resource = 0; |
| 226 | free_reg = 0; |
| 227 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 228 | int result; |
| 229 | result = reg_useable(reg, dev, nodeid, link); |
| 230 | if (result == 1) { |
| 231 | /* I have been allocated this one */ |
| 232 | break; |
| 233 | } |
| 234 | else if (result > 1) { |
| 235 | /* I have a free register pair */ |
| 236 | free_reg = reg; |
| 237 | } |
| 238 | } |
| 239 | if (reg > 0xb8) { |
| 240 | reg = free_reg; |
| 241 | } |
| 242 | |
| 243 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 244 | return resource; |
| 245 | } |
| 246 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 247 | static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 248 | { |
| 249 | struct resource *resource; |
| 250 | |
| 251 | /* Initialize the io space constraints on the current bus */ |
| 252 | resource = amdfam16_find_iopair(dev, nodeid, link); |
| 253 | if (resource) { |
| 254 | u32 align; |
| 255 | align = log2(HT_IO_HOST_ALIGN); |
| 256 | resource->base = 0; |
| 257 | resource->size = 0; |
| 258 | resource->align = align; |
| 259 | resource->gran = align; |
| 260 | resource->limit = 0xffffUL; |
| 261 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 262 | } |
| 263 | |
| 264 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 265 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 266 | if (resource) { |
| 267 | resource->base = 0; |
| 268 | resource->size = 0; |
| 269 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 270 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 271 | resource->limit = 0xffffffffffULL; |
| 272 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 273 | resource->flags |= IORESOURCE_BRIDGE; |
| 274 | } |
| 275 | |
| 276 | /* Initialize the memory constraints on the current bus */ |
| 277 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 278 | if (resource) { |
| 279 | resource->base = 0; |
| 280 | resource->size = 0; |
| 281 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 282 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 283 | resource->limit = 0xffffffffffULL; |
| 284 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 285 | } |
| 286 | |
| 287 | } |
| 288 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 289 | static void read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 290 | { |
| 291 | u32 nodeid; |
| 292 | struct bus *link; |
| 293 | |
| 294 | nodeid = amdfam16_nodeid(dev); |
| 295 | for (link = dev->link_list; link; link = link->next) { |
| 296 | if (link->children) { |
| 297 | amdfam16_link_read_bases(dev, nodeid, link->link_num); |
| 298 | } |
| 299 | } |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 300 | |
| 301 | /* |
| 302 | * This MMCONF resource must be reserved in the PCI domain. |
| 303 | * It is not honored by the coreboot resource allocator if it is in |
| 304 | * the CPU_CLUSTER. |
| 305 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 306 | mmconf_resource(dev, MMIO_CONF_BASE); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 307 | } |
| 308 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 309 | static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 310 | { |
| 311 | resource_t rbase, rend; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 312 | unsigned int reg, link_num; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 313 | char buf[50]; |
| 314 | |
| 315 | /* Make certain the resource has actually been set */ |
| 316 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 317 | return; |
| 318 | } |
| 319 | |
| 320 | /* If I have already stored this resource don't worry about it */ |
| 321 | if (resource->flags & IORESOURCE_STORED) { |
| 322 | return; |
| 323 | } |
| 324 | |
| 325 | /* Only handle PCI memory and IO resources */ |
| 326 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 327 | return; |
| 328 | |
| 329 | /* Ensure I am actually looking at a resource of function 1 */ |
| 330 | if ((resource->index & 0xffff) < 0x1000) { |
| 331 | return; |
| 332 | } |
| 333 | /* Get the base address */ |
| 334 | rbase = resource->base; |
| 335 | |
| 336 | /* Get the limit (rounded up) */ |
| 337 | rend = resource_end(resource); |
| 338 | |
| 339 | /* Get the register and link */ |
| 340 | reg = resource->index & 0xfff; // 4k |
| 341 | link_num = IOINDEX_LINK(resource->index); |
| 342 | |
| 343 | if (resource->flags & IORESOURCE_IO) { |
| 344 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 345 | } |
| 346 | else if (resource->flags & IORESOURCE_MEM) { |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 347 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 348 | } |
| 349 | resource->flags |= IORESOURCE_STORED; |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 350 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 351 | nodeid, link_num); |
| 352 | report_resource_stored(dev, resource, buf); |
| 353 | } |
| 354 | |
| 355 | /** |
| 356 | * I tried to reuse the resource allocation code in set_resource() |
| 357 | * but it is too difficult to deal with the resource allocation magic. |
| 358 | */ |
| 359 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 360 | static void create_vga_resource(struct device *dev, unsigned int nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 361 | { |
| 362 | struct bus *link; |
| 363 | |
| 364 | /* find out which link the VGA card is connected, |
| 365 | * we only deal with the 'first' vga card */ |
| 366 | for (link = dev->link_list; link; link = link->next) { |
| 367 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 368 | #if CONFIG(MULTIPLE_VGA_ADAPTERS) |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 369 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 370 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 371 | link->secondary,link->subordinate); |
| 372 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 373 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 374 | (vga_pri->bus->secondary <= link->subordinate)) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 375 | #endif |
| 376 | break; |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | /* no VGA card installed */ |
| 381 | if (link == NULL) |
| 382 | return; |
| 383 | |
| 384 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 385 | set_vga_enable_reg(nodeid, sblink); |
| 386 | } |
| 387 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 388 | static void set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 389 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 390 | unsigned int nodeid; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 391 | struct bus *bus; |
| 392 | struct resource *res; |
| 393 | |
| 394 | /* Find the nodeid */ |
| 395 | nodeid = amdfam16_nodeid(dev); |
| 396 | |
| 397 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 398 | |
| 399 | /* Set each resource we have found */ |
| 400 | for (res = dev->resource_list; res; res = res->next) { |
| 401 | set_resource(dev, res, nodeid); |
| 402 | } |
| 403 | |
| 404 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 405 | if (bus->children) { |
| 406 | assign_resources(bus); |
| 407 | } |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | static void northbridge_init(struct device *dev) |
| 412 | { |
| 413 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 414 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 415 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 416 | { |
| 417 | void *addr, *current; |
| 418 | |
| 419 | /* Skip the HEST header. */ |
| 420 | current = (void *)(hest + 1); |
| 421 | |
| 422 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 423 | if (addr != NULL) |
| 424 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 425 | |
| 426 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 427 | if (addr != NULL) |
| 428 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 429 | |
| 430 | return (unsigned long)current; |
| 431 | } |
| 432 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 433 | static void add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 434 | unsigned long *current, uint16_t *length, |
| 435 | uint8_t type, uint8_t data) |
| 436 | { |
| 437 | uint8_t *p; |
| 438 | p = (uint8_t *) *current; |
| 439 | |
| 440 | if (type == 0x2) { |
| 441 | /* Entry type */ |
| 442 | p[0] = type; |
| 443 | /* Device */ |
| 444 | p[1] = dev->path.pci.devfn; |
| 445 | /* Bus */ |
| 446 | p[2] = dev->bus->secondary; |
| 447 | /* Data */ |
| 448 | p[3] = data; |
| 449 | /* [4:7] Padding */ |
| 450 | p[4] = 0x0; |
| 451 | p[5] = 0x0; |
| 452 | p[6] = 0x0; |
| 453 | p[7] = 0x0; |
| 454 | *length += 8; |
| 455 | *current += 8; |
| 456 | } else if (type == 0x42) { |
| 457 | /* Entry type */ |
| 458 | p[0] = type; |
| 459 | /* Device */ |
| 460 | p[1] = dev->path.pci.devfn; |
| 461 | /* Bus */ |
| 462 | p[2] = dev->bus->secondary; |
| 463 | /* Data */ |
| 464 | p[3] = 0x0; |
| 465 | /* Reserved */ |
| 466 | p[4] = 0x0; |
| 467 | /* Device */ |
| 468 | p[5] = parent->path.pci.devfn; |
| 469 | /* Bus */ |
| 470 | p[6] = parent->bus->secondary; |
| 471 | /* Reserved */ |
| 472 | p[7] = 0x0; |
| 473 | *length += 8; |
| 474 | *current += 8; |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | static void add_ivrs_device_entries(struct device *parent, struct device *dev, |
| 479 | unsigned int depth, int linknum, int8_t *root_level, |
| 480 | unsigned long *current, uint16_t *length) |
| 481 | { |
| 482 | struct device *sibling; |
| 483 | struct bus *link; |
| 484 | unsigned int header_type; |
| 485 | unsigned int is_pcie; |
| 486 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 487 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 488 | |
| 489 | if ((dev->bus->secondary == 0x0) && |
| 490 | (dev->path.pci.devfn == 0x0)) |
| 491 | *root_level = depth; |
| 492 | |
| 493 | if ((*root_level != -1) && (dev->enabled)) { |
| 494 | if (depth == *root_level) { |
| 495 | if (dev->path.pci.devfn == (0x14 << 3)) { |
| 496 | /* SMBUS controller */ |
| 497 | add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x97); |
| 498 | } else if (dev->path.pci.devfn != 0x2 && |
| 499 | dev->path.pci.devfn < (0x2 << 3)) { |
| 500 | /* FCH control device */ |
| 501 | } else { |
| 502 | /* Other devices */ |
| 503 | add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); |
| 504 | } |
| 505 | } else { |
| 506 | header_type = dev->hdr_type & 0x7f; |
| 507 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 508 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 509 | (header_type == PCI_HEADER_TYPE_BRIDGE)) |
| 510 | && is_pcie) { |
| 511 | /* Device or Bridge is PCIe */ |
| 512 | add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); |
| 513 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && |
| 514 | !is_pcie) { |
| 515 | add_ivhd_dev_entry(parent, dev, current, length, 0x42, 0x0); |
| 516 | /* Device is legacy PCI or PCI-X */ |
| 517 | } |
| 518 | } |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | for (link = dev->link_list; link; link = link->next) |
| 523 | for (sibling = link->children; sibling; sibling = |
| 524 | sibling->sibling) |
| 525 | add_ivrs_device_entries(dev, sibling, depth + 1, depth, |
| 526 | root_level, current, length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
| 530 | { |
| 531 | uint8_t *p; |
| 532 | |
| 533 | uint32_t apicid_sb800; |
| 534 | uint32_t apicid_northbridge; |
| 535 | |
| 536 | apicid_sb800 = CONFIG_MAX_CPUS; |
| 537 | apicid_northbridge = CONFIG_MAX_CPUS + 1; |
| 538 | |
| 539 | /* Describe NB IOAPIC */ |
| 540 | p = (uint8_t *)current; |
| 541 | p[0] = 0x48; /* Entry type */ |
| 542 | p[1] = 0; /* Device */ |
| 543 | p[2] = 0; /* Bus */ |
| 544 | p[3] = 0x0; /* Data */ |
| 545 | p[4] = apicid_northbridge; /* IOAPIC ID */ |
| 546 | p[5] = 0x0; /* Device 0 Function 0 */ |
| 547 | p[6] = 0x0; /* Northbridge bus */ |
| 548 | p[7] = 0x1; /* Variety */ |
| 549 | current += 8; |
| 550 | |
| 551 | /* Describe SB IOAPIC */ |
| 552 | p = (uint8_t *)current; |
| 553 | p[0] = 0x48; /* Entry type */ |
| 554 | p[1] = 0; /* Device */ |
| 555 | p[2] = 0; /* Bus */ |
| 556 | p[3] = 0xd7; /* Data */ |
| 557 | p[4] = apicid_sb800; /* IOAPIC ID */ |
| 558 | p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ |
| 559 | p[6] = 0x0; /* Southbridge bus */ |
| 560 | p[7] = 0x1; /* Variety */ |
| 561 | current += 8; |
| 562 | |
| 563 | return current; |
| 564 | } |
| 565 | |
| 566 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 567 | { |
| 568 | uint8_t *p; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 569 | acpi_ivrs_t *ivrs_agesa; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 570 | |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 571 | struct device *nb_dev = pcidev_on_root(0x0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 572 | if (!nb_dev) { |
| 573 | |
| 574 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 575 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 576 | |
| 577 | return (unsigned long)ivrs; |
| 578 | } |
| 579 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 580 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 581 | /* obtain IOMMU base address */ |
| 582 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 583 | if (ivrs_agesa != NULL) { |
| 584 | ivrs->iv_info = 0x0; |
| 585 | /* Maximum supported virtual address size */ |
| 586 | ivrs->iv_info |= (0x40 << 15); |
| 587 | /* Maximum supported physical address size */ |
| 588 | ivrs->iv_info |= (0x30 << 8); |
| 589 | /* Guest virtual address width */ |
| 590 | ivrs->iv_info |= (0x2 << 5); |
| 591 | |
| 592 | ivrs->ivhd.type = 0x10; |
| 593 | ivrs->ivhd.flags = 0x0e; |
| 594 | /* Enable ATS support */ |
| 595 | ivrs->ivhd.flags |= 0x10; |
| 596 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 597 | /* BDF <bus>:00.2 */ |
| 598 | ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); |
| 599 | /* Capability block 0x40 (type 0xf, "Secure device") */ |
| 600 | ivrs->ivhd.capability_offset = 0x40; |
| 601 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 602 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 603 | ivrs->ivhd.pci_segment_group = 0x0; |
| 604 | ivrs->ivhd.iommu_info = 0x0; |
| 605 | ivrs->ivhd.iommu_info |= (0x13 << 8); |
| 606 | /* use only performance counters related bits: |
| 607 | * PNCounters[16:13] and |
| 608 | * PNBanks[22:17], |
| 609 | * otherwise 0 */ |
| 610 | ivrs->ivhd.iommu_feature_info = |
| 611 | ivrs_agesa->ivhd.iommu_feature_info & 0x7fe000; |
| 612 | } else { |
| 613 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 614 | |
| 615 | return (unsigned long)ivrs; |
| 616 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 617 | |
| 618 | /* Describe HPET */ |
| 619 | p = (uint8_t *)current; |
| 620 | p[0] = 0x48; /* Entry type */ |
| 621 | p[1] = 0; /* Device */ |
| 622 | p[2] = 0; /* Bus */ |
| 623 | p[3] = 0xd7; /* Data */ |
| 624 | p[4] = 0x0; /* HPET number */ |
| 625 | p[5] = 0x14 << 3; /* HPET device */ |
| 626 | p[6] = nb_dev->bus->secondary; /* HPET bus */ |
| 627 | p[7] = 0x2; /* Variety */ |
| 628 | ivrs->ivhd.length += 8; |
| 629 | current += 8; |
| 630 | |
| 631 | /* Describe PCI devices */ |
Jacob Garber | 293e6a9 | 2019-07-17 11:47:19 -0600 | [diff] [blame] | 632 | int8_t root_level = -1; |
| 633 | add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, ¤t, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 634 | &ivrs->ivhd.length); |
| 635 | |
| 636 | /* Describe IOAPICs */ |
| 637 | unsigned long prev_current = current; |
| 638 | current = acpi_fill_ivrs_ioapic(ivrs, current); |
| 639 | ivrs->ivhd.length += (current - prev_current); |
| 640 | |
| 641 | return current; |
| 642 | } |
| 643 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 644 | static void northbridge_fill_ssdt_generator(struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 645 | { |
| 646 | msr_t msr; |
| 647 | char pscope[] = "\\_SB.PCI0"; |
| 648 | |
| 649 | acpigen_write_scope(pscope); |
| 650 | msr = rdmsr(TOP_MEM); |
| 651 | acpigen_write_name_dword("TOM1", msr.lo); |
| 652 | msr = rdmsr(TOP_MEM2); |
| 653 | /* |
| 654 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 655 | * here. |
| 656 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 657 | * slide 22ff. |
| 658 | * Shift value right by 20 bit to make it fit into 32bit, |
| 659 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 660 | */ |
| 661 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 662 | acpigen_pop_len(); |
| 663 | } |
| 664 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 665 | static unsigned long agesa_write_acpi_tables(struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 666 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 667 | acpi_rsdp_t *rsdp) |
| 668 | { |
| 669 | acpi_srat_t *srat; |
| 670 | acpi_slit_t *slit; |
| 671 | acpi_header_t *ssdt; |
| 672 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 673 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 674 | |
| 675 | /* HEST */ |
| 676 | current = ALIGN(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 677 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 678 | acpi_add_table(rsdp, (void *)current); |
| 679 | current += ((acpi_header_t *)current)->length; |
| 680 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 681 | /* IVRS */ |
| 682 | current = ALIGN(current, 8); |
| 683 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 684 | ivrs = (acpi_ivrs_t *) current; |
| 685 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 686 | current += ivrs->header.length; |
| 687 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 688 | |
| 689 | /* SRAT */ |
| 690 | current = ALIGN(current, 8); |
| 691 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 692 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 693 | if (srat != NULL) { |
| 694 | memcpy((void *)current, srat, srat->header.length); |
| 695 | srat = (acpi_srat_t *) current; |
| 696 | current += srat->header.length; |
| 697 | acpi_add_table(rsdp, srat); |
| 698 | } else { |
| 699 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 700 | } |
| 701 | |
| 702 | /* SLIT */ |
| 703 | current = ALIGN(current, 8); |
| 704 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 705 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 706 | if (slit != NULL) { |
| 707 | memcpy((void *)current, slit, slit->header.length); |
| 708 | slit = (acpi_slit_t *) current; |
| 709 | current += slit->header.length; |
| 710 | acpi_add_table(rsdp, slit); |
| 711 | } else { |
| 712 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 713 | } |
| 714 | |
| 715 | /* ALIB */ |
| 716 | current = ALIGN(current, 16); |
| 717 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 718 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 719 | if (alib != NULL) { |
| 720 | memcpy((void *)current, alib, alib->length); |
| 721 | alib = (acpi_header_t *) current; |
| 722 | current += alib->length; |
| 723 | acpi_add_table(rsdp, (void *)alib); |
| 724 | } |
| 725 | else { |
| 726 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 727 | } |
| 728 | |
| 729 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 730 | /* SSDT */ |
| 731 | current = ALIGN(current, 16); |
| 732 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 733 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 734 | if (ssdt != NULL) { |
| 735 | memcpy((void *)current, ssdt, ssdt->length); |
| 736 | ssdt = (acpi_header_t *) current; |
| 737 | current += ssdt->length; |
| 738 | } |
| 739 | else { |
| 740 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 741 | } |
| 742 | acpi_add_table(rsdp,ssdt); |
| 743 | |
| 744 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 745 | return current; |
| 746 | } |
| 747 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 748 | static struct device_operations northbridge_operations = { |
| 749 | .read_resources = read_resources, |
| 750 | .set_resources = set_resources, |
| 751 | .enable_resources = pci_dev_enable_resources, |
| 752 | .init = northbridge_init, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 753 | .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, |
| 754 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 755 | .enable = 0, |
| 756 | .ops_pci = 0, |
| 757 | }; |
| 758 | |
| 759 | static const struct pci_driver family16_northbridge __pci_driver = { |
| 760 | .ops = &northbridge_operations, |
| 761 | .vendor = PCI_VENDOR_ID_AMD, |
Marshall Dawson | 463f46e | 2016-10-14 20:46:08 -0600 | [diff] [blame] | 762 | .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 763 | }; |
| 764 | |
| 765 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 766 | .ops = &northbridge_operations, |
| 767 | .vendor = PCI_VENDOR_ID_AMD, |
| 768 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 769 | }; |
| 770 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 771 | static void fam16_finalize(void *chip_info) |
| 772 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 773 | struct device *dev; |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 774 | u32 value; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 775 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 776 | pci_write_config32(dev, 0xF8, 0); |
| 777 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 778 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 779 | /* |
| 780 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 781 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 782 | * right function that enables these functionalities. Disabled ACS |
| 783 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 784 | * group. Without IOMMU group separation the devices cannot be passed |
| 785 | * through independently. |
| 786 | */ |
| 787 | |
| 788 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 789 | pci_write_config32(dev, 0xE0, 0x014000B0); |
| 790 | value = pci_read_config32(dev, 0xE4); |
| 791 | |
| 792 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
| 793 | value |= PCIE_CAP_AER | PCIE_CAP_ACS; |
| 794 | pci_write_config32(dev, 0xE4, value); |
| 795 | |
| 796 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 797 | pci_write_config32(dev, 0xE0, 0x01300000); |
| 798 | value = pci_read_config32(dev, 0xE4); |
| 799 | |
| 800 | /* |
| 801 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 802 | * looks like these bits enable: Source Validation and Translation |
| 803 | * Blocking |
| 804 | */ |
| 805 | value |= (BIT(24) | BIT(25) | BIT(26)); |
| 806 | pci_write_config32(dev, 0xE4, value); |
| 807 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 808 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 809 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 810 | if (dev != NULL) { |
| 811 | value = pci_read_config32(dev, 0x60); |
| 812 | value &= ~(1 << 11); |
| 813 | pci_write_config32(dev, 0x60, value); |
| 814 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 815 | } |
| 816 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 817 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 818 | CHIP_NAME("AMD FAM16 Northbridge") |
| 819 | .enable_dev = 0, |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 820 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 821 | }; |
| 822 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 823 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 824 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 825 | unsigned int reg; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 826 | |
| 827 | /* Find the already assigned resource pairs */ |
| 828 | get_fx_devs(); |
| 829 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 830 | u32 base, limit; |
| 831 | base = f1_read_config32(reg); |
| 832 | limit = f1_read_config32(reg + 0x04); |
| 833 | /* Is this register allocated? */ |
| 834 | if ((base & 3) != 0) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 835 | unsigned int nodeid, reg_link; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 836 | struct device *reg_dev; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 837 | if (reg < 0xc0) { // mmio |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 838 | nodeid = (limit & 0xf) + (base&0x30); |
| 839 | } else { // io |
| 840 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 841 | } |
| 842 | reg_link = (limit >> 4) & 7; |
| 843 | reg_dev = __f0_dev[nodeid]; |
| 844 | if (reg_dev) { |
| 845 | /* Reserve the resource */ |
| 846 | struct resource *res; |
| 847 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 848 | if (res) { |
| 849 | res->flags = 1; |
| 850 | } |
| 851 | } |
| 852 | } |
| 853 | } |
| 854 | /* FIXME: do we need to check extend conf space? |
| 855 | I don't believe that much preset value */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 856 | pci_domain_read_resources(dev); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 857 | } |
| 858 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 859 | static void domain_enable_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 860 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 861 | } |
| 862 | |
| 863 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 864 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 865 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 866 | int node_id; |
| 867 | }; |
| 868 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 869 | { |
| 870 | struct hw_mem_hole_info mem_hole; |
| 871 | int i; |
| 872 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 873 | mem_hole.node_id = -1; |
| 874 | for (i = 0; i < node_nums; i++) { |
| 875 | dram_base_mask_t d; |
| 876 | u32 hole; |
| 877 | d = get_dram_base_mask(i); |
| 878 | if (!(d.mask & 1)) continue; // no memory on this node |
| 879 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 880 | if (hole & 2) { // we find the hole |
| 881 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 882 | mem_hole.node_id = i; // record the node No with hole |
| 883 | break; // only one hole |
| 884 | } |
| 885 | } |
| 886 | |
| 887 | /* We need to double check if there is special set on base reg and limit reg |
| 888 | * are not continuous instead of hole, it will find out its hole_startk. |
| 889 | */ |
| 890 | if (mem_hole.node_id == -1) { |
| 891 | resource_t limitk_pri = 0; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 892 | for (i = 0; i < node_nums; i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 893 | dram_base_mask_t d; |
| 894 | resource_t base_k, limit_k; |
| 895 | d = get_dram_base_mask(i); |
| 896 | if (!(d.base & 1)) continue; |
| 897 | base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; |
| 898 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 899 | if (limitk_pri != base_k) { // we find the hole |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 900 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 901 | mem_hole.node_id = i; |
| 902 | break; //only one hole |
| 903 | } |
| 904 | limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
| 905 | limitk_pri = limit_k; |
| 906 | } |
| 907 | } |
| 908 | return mem_hole; |
| 909 | } |
| 910 | #endif |
| 911 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 912 | static void domain_set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 913 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 914 | unsigned long mmio_basek; |
| 915 | u32 pci_tolm; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 916 | int i, idx; |
| 917 | struct bus *link; |
| 918 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 919 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 920 | #endif |
| 921 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 922 | pci_tolm = 0xffffffffUL; |
| 923 | for (link = dev->link_list; link; link = link->next) { |
| 924 | pci_tolm = find_pci_tolm(link); |
| 925 | } |
| 926 | |
| 927 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 928 | // amdk8, too. |
| 929 | mmio_basek = pci_tolm >> 10; |
| 930 | /* Round mmio_basek to something the processor can support */ |
| 931 | mmio_basek &= ~((1 << 6) -1); |
| 932 | |
| 933 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 934 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 935 | /* Round the mmio hole to 64M */ |
| 936 | mmio_basek &= ~((64*1024) - 1); |
| 937 | |
| 938 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 939 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 940 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 941 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 942 | * otherwise We reset the hole to the mmio_basek |
| 943 | */ |
| 944 | |
| 945 | mem_hole = get_hw_mem_hole_info(); |
| 946 | |
| 947 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 948 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 949 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 950 | } |
| 951 | #endif |
| 952 | |
| 953 | idx = 0x10; |
| 954 | for (i = 0; i < node_nums; i++) { |
| 955 | dram_base_mask_t d; |
| 956 | resource_t basek, limitk, sizek; // 4 1T |
| 957 | |
| 958 | d = get_dram_base_mask(i); |
| 959 | |
| 960 | if (!(d.mask & 1)) continue; |
| 961 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 962 | limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 963 | |
| 964 | sizek = limitk - basek; |
| 965 | |
| 966 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 967 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 968 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 969 | idx += 0x10; |
| 970 | basek = (8*64)+(16*16); |
| 971 | sizek = limitk - ((8*64)+(16*16)); |
| 972 | |
| 973 | } |
| 974 | |
| 975 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 976 | |
| 977 | /* split the region to accommodate pci memory space */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 978 | if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 979 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 980 | unsigned int pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 981 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 982 | if (pre_sizek > 0) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 983 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 984 | idx += 0x10; |
| 985 | sizek -= pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 986 | } |
| 987 | basek = mmio_basek; |
| 988 | } |
| 989 | if ((basek + sizek) <= 4*1024*1024) { |
| 990 | sizek = 0; |
| 991 | } |
| 992 | else { |
| 993 | uint64_t topmem2 = bsp_topmem2(); |
| 994 | basek = 4*1024*1024; |
| 995 | sizek = topmem2/1024 - basek; |
| 996 | } |
| 997 | } |
| 998 | |
| 999 | ram_resource(dev, (idx | i), basek, sizek); |
| 1000 | idx += 0x10; |
| 1001 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 1002 | i, mmio_basek, basek, limitk); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1003 | } |
| 1004 | |
Kyösti Mälkki | e87564f | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 1005 | add_uma_resource_below_tolm(dev, 7); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1006 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1007 | for (link = dev->link_list; link; link = link->next) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1008 | if (link->children) { |
| 1009 | assign_resources(link); |
| 1010 | } |
| 1011 | } |
| 1012 | } |
| 1013 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 1014 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1015 | { |
| 1016 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 1017 | return "PCI0"; |
| 1018 | |
| 1019 | return NULL; |
| 1020 | } |
| 1021 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1022 | static struct device_operations pci_domain_ops = { |
| 1023 | .read_resources = domain_read_resources, |
| 1024 | .set_resources = domain_set_resources, |
| 1025 | .enable_resources = domain_enable_resources, |
| 1026 | .init = NULL, |
| 1027 | .scan_bus = pci_domain_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1028 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1029 | }; |
| 1030 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1031 | static void sysconf_init(struct device *dev) // first node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1032 | { |
| 1033 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 1034 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 1035 | } |
| 1036 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1037 | static void cpu_bus_scan(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1038 | { |
| 1039 | struct bus *cpu_bus; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1040 | struct device *dev_mc; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1041 | int i,j; |
| 1042 | int coreid_bits; |
| 1043 | int core_max = 0; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1044 | unsigned int ApicIdCoreIdSize; |
| 1045 | unsigned int core_nums; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1046 | int siblings = 0; |
| 1047 | unsigned int family; |
| 1048 | u32 modules = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1049 | int ioapic_count = 0; |
| 1050 | |
Michał Żygowski | e719288 | 2019-11-23 19:02:19 +0100 | [diff] [blame] | 1051 | /* For binaryPI there is no multiprocessor configuration, the number of |
| 1052 | * modules will always be 1. */ |
| 1053 | modules = 1; |
| 1054 | ioapic_count = CONFIG_NUM_OF_IOAPICS; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1055 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1056 | dev_mc = pcidev_on_root(DEV_CDB, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1057 | if (!dev_mc) { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1058 | printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1059 | die(""); |
| 1060 | } |
| 1061 | sysconf_init(dev_mc); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1062 | |
| 1063 | /* Get Max Number of cores(MNC) */ |
Kyösti Mälkki | d41feed | 2017-09-24 16:23:57 +0300 | [diff] [blame] | 1064 | coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1065 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 1066 | |
| 1067 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 1068 | if (ApicIdCoreIdSize) { |
| 1069 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 1070 | } else { |
| 1071 | core_nums = 3; //quad core |
| 1072 | } |
| 1073 | |
| 1074 | /* Find which cpus are present */ |
| 1075 | cpu_bus = dev->link_list; |
| 1076 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1077 | struct device *cdb_dev; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1078 | unsigned int devn; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1079 | struct bus *pbus; |
| 1080 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1081 | devn = DEV_CDB + i; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1082 | pbus = dev_mc->bus; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1083 | |
| 1084 | /* Find the cpu's pci device */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1085 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1086 | if (!cdb_dev) { |
| 1087 | /* If I am probing things in a weird order |
| 1088 | * ensure all of the cpu's pci devices are found. |
| 1089 | */ |
| 1090 | int fn; |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1091 | for (fn = 0; fn <= 5; fn++) { //FBDIMM? |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1092 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 1093 | PCI_DEVFN(devn, fn)); |
| 1094 | } |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1095 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1096 | } else { |
| 1097 | /* Ok, We need to set the links for that device. |
| 1098 | * otherwise the device under it will not be scanned |
| 1099 | */ |
Kyösti Mälkki | c5163ed8 | 2015-02-04 13:25:37 +0200 | [diff] [blame] | 1100 | |
| 1101 | add_more_links(cdb_dev, 4); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1102 | } |
| 1103 | |
| 1104 | family = cpuid_eax(1); |
| 1105 | family = (family >> 20) & 0xFF; |
| 1106 | if (family == 1) { //f10 |
| 1107 | u32 dword; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1108 | cdb_dev = pcidev_on_root(devn, 3); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1109 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 1110 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 1111 | } else if (family == 7) {//f16 |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1112 | cdb_dev = pcidev_on_root(devn, 5); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1113 | if (cdb_dev && cdb_dev->enabled) { |
| 1114 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 1115 | siblings &= 0xFF; |
| 1116 | } |
| 1117 | } else { |
| 1118 | siblings = 0; //default one core |
| 1119 | } |
| 1120 | int enable_node = cdb_dev && cdb_dev->enabled; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1121 | printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1122 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 1123 | |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1124 | for (j = 0; j <= siblings; j++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1125 | u32 lapicid_start = 0; |
| 1126 | |
| 1127 | /* |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 1128 | * APIC ID calculation is tightly coupled with AGESA v5 code. |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1129 | * This calculation MUST match the assignment calculation done |
| 1130 | * in LocalApicInitializationAtEarly() function. |
| 1131 | * And reference GetLocalApicIdForCore() |
| 1132 | * |
Elyes HAOUAS | a5b0bc4 | 2020-02-20 20:04:29 +0100 | [diff] [blame^] | 1133 | * Apply APIC enumeration rules |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1134 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 1135 | * put the local-APICs at m..z |
| 1136 | * |
| 1137 | * This is needed because many IO-APIC devices only have 4 bits |
| 1138 | * for their APIC id and therefore must reside at 0..15 |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 1139 | */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1140 | if ((node_nums * core_max) + ioapic_count >= 0x10) { |
| 1141 | lapicid_start = (ioapic_count - 1) / core_max; |
| 1142 | lapicid_start = (lapicid_start + 1) * core_max; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1143 | printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1144 | } |
| 1145 | u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1146 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1147 | i, j, apic_id); |
| 1148 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1149 | struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1150 | if (cpu) |
| 1151 | amd_cpu_topology(cpu, i, j); |
| 1152 | } //j |
| 1153 | } |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1154 | } |
| 1155 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1156 | static void cpu_bus_init(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1157 | { |
| 1158 | initialize_cpus(dev->link_list); |
| 1159 | } |
| 1160 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1161 | static struct device_operations cpu_bus_ops = { |
Kyösti Mälkki | 48f82a9 | 2016-12-02 16:02:30 +0200 | [diff] [blame] | 1162 | .read_resources = DEVICE_NOOP, |
| 1163 | .set_resources = DEVICE_NOOP, |
Edward O'Callaghan | 812d2a4 | 2014-10-31 08:17:23 +1100 | [diff] [blame] | 1164 | .enable_resources = DEVICE_NOOP, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1165 | .init = cpu_bus_init, |
| 1166 | .scan_bus = cpu_bus_scan, |
| 1167 | }; |
| 1168 | |
| 1169 | static void root_complex_enable_dev(struct device *dev) |
| 1170 | { |
| 1171 | static int done = 0; |
| 1172 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1173 | if (!done) { |
| 1174 | setup_bsp_ramtop(); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1175 | done = 1; |
| 1176 | } |
| 1177 | |
| 1178 | /* Set the operations if it is a special bus type */ |
| 1179 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 1180 | dev->ops = &pci_domain_ops; |
| 1181 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 1182 | dev->ops = &cpu_bus_ops; |
| 1183 | } |
| 1184 | } |
| 1185 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1186 | struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1187 | CHIP_NAME("AMD FAM16 Root Complex") |
| 1188 | .enable_dev = root_complex_enable_dev, |
| 1189 | }; |
| 1190 | |
| 1191 | /********************************************************************* |
| 1192 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 1193 | *********************************************************************/ |
| 1194 | u32 map_oprom_vendev(u32 vendev) |
| 1195 | { |
| 1196 | u32 new_vendev; |
| 1197 | new_vendev = |
| 1198 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 1199 | |
| 1200 | if (vendev != new_vendev) |
| 1201 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 1202 | |
| 1203 | return new_vendev; |
| 1204 | } |