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review.coreboot.org / coreboot / 86bc2e708dc2600c5611b6573d43645e7d57e561 / . / src / southbridge / intel / i82801ix / acpi / ich9.asl
blob: 53339b4512967b1253ab1075b318b0398308e24c [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]2
3/* Intel 82801Ix support */
4
5Scope(\)
6{
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]7 // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
8 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
9 Field(PMIO, ByteAcc, NoLock, Preserve)
10 {
11 Offset(0x11),
12 THRO, 1, // force thermal throttling
13 Offset(0x42), // General Purpose Control
14 , 1, // skip 1 bit
15 GPEC, 1, // TCO status
16 Offset(0x64),
17 , 9, // skip 9 more bits
18 SCIS, 1 // TCO DMI status
19 }
20
21 // FIXME: purposes of the GPIOs (comments) are probably wrong
22 // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
23 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
24 Field(GPIO, ByteAcc, NoLock, Preserve)
25 {
Elyes HAOUAS48a6c012020-07-08 09:22:13 +0200[diff] [blame]26 GU00, 8, // GPIO Use Select
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]27 GU01, 8,
28 GU02, 8,
29 GU03, 8,
30 Offset(0x04), // GPIO IO Select
31 GIO0, 8,
32 GIO1, 8,
33 GIO2, 8,
34 GIO3, 8,
35 Offset(0x0c), // GPIO Level
36 GP00, 1,
37 GP01, 1,
38 GP02, 1,
39 GP03, 1,
40 GP04, 1,
41 GP05, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]42 GP06, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]43 GP07, 1,
44 GP08, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]45 GP09, 1,
46 GP10, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]47 GP11, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]48 GP12, 1,
49 GP13, 1,
50 GP14, 1,
51 GP15, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]52 GP16, 1,
53 GP17, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]54 GP18, 1,
55 GP19, 1,
56 GP20, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]57 GP21, 1,
58 GP22, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]59 GP23, 1,
60 GP24, 1,
61 GP25, 1,
62 GP26, 1,
63 GP27, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]64 GP28, 1,
65 GP29, 1,
66 GP30, 1,
67 GP31, 1,
68 Offset(0x18), // GPIO Blink
69 GB00, 8,
70 GB01, 8,
71 GB02, 8,
72 GB03, 8,
73 Offset(0x2c), // GPIO Invert
74 GIV0, 8,
75 GIV1, 8,
76 GIV2, 8,
77 GIV3, 8,
78 Offset(0x30), // GPIO Use Select 2
79 GU04, 8,
80 GU05, 8,
81 GU06, 8,
82 GU07, 8,
83 Offset(0x34), // GPIO IO Select 2
84 GIO4, 8,
85 GIO5, 8,
86 GIO6, 8,
87 GIO7, 8,
88 Offset(0x38), // GPIO Level 2
89 GP32, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]90 GP33, 1,
91 GP34, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]92 GP35, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]93 GP36, 1,
94 GP37, 1,
95 GP38, 1,
96 GP39, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]97 GL05, 8,
98 GL06, 8,
99 GL07, 8
100 }
101
102
103 // ICH9 Root Complex Register Block. Memory Mapped through RCBA)
Angel Ponsb70ff522021-01-28 14:27:46 +0100[diff] [blame]104 OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]105 Field(RCRB, DWordAcc, Lock, Preserve)
106 {
107 Offset(0x0000), // Backbone
108 Offset(0x1000), // Chipset
109 Offset(0x3000), // Legacy Configuration Registers
110 Offset(0x3404), // High Performance Timer Configuration
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200[diff] [blame]111 HPAS, 2, // Address Select
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]112 , 5,
113 HPTE, 1, // Address Enable
114 Offset(0x3418), // FD (Function Disable)
115 , 2, // Reserved
116 SA1D, 1, // SATA disable
117 SMBD, 1, // SMBUS disable
118 HDAD, 1, // Azalia disable
119 , 2, // Reserved
120 US6D, 1, // UHCI #6 disable
121 US1D, 1, // UHCI #1 disable
122 US2D, 1, // UHCI #2 disable
123 US3D, 1, // UHCI #3 disable
124 US4D, 1, // UHCI #4 disable
125 US5D, 1, // UHCI #5 disable
126 EH2D, 1, // EHCI disable
127 LPBD, 1, // LPC bridge disable
128 EH1D, 1, // EHCI disable
129 Offset(0x341a), // FD Root Ports
130 RP1D, 1, // Root Port 1 disable
131 RP2D, 1, // Root Port 2 disable
132 RP3D, 1, // Root Port 3 disable
133 RP4D, 1, // Root Port 4 disable
134 RP5D, 1, // Root Port 5 disable
135 RP6D, 1, // Root Port 6 disable
136 , 2, // Reserved
137 THRD, 1, // Thermal Throttle disable
138 SA2D, 1, // SATA disable
139 }
140
141}
142
143// 0:1b.0 High Definition Audio (Azalia)
Angel Ponsb6427b02020-07-07 01:29:40 +0200[diff] [blame]144#include <southbridge/intel/common/acpi/audio_ich.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]145
146// PCI Express Ports
Arthur Heymansdff185a2018-12-30 12:59:39 +0100[diff] [blame]147#include <southbridge/intel/common/acpi/pcie.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]148
149// USB
150#include "usb.asl"
151
152// PCI Bridge
153#include "pci.asl"
154
155// LPC Bridge
156#include "lpc.asl"
157
158// SATA
159#include "sata.asl"
160
161// SMBus
Elyes HAOUAS085ab5a2019-10-31 10:12:02 +0100[diff] [blame]162#include <southbridge/intel/common/acpi/smbus.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]163
164Method (_OSC, 4)
165{
166 /* Check for proper GUID */
Felix Singer644e59b2022-01-02 01:21:34 +0100[diff] [blame]167 If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]168 {
169 /* Let OS control everything */
170 Return (Arg3)
171 }
172 Else
173 {
174 /* Unrecognized UUID */
175 CreateDWordField (Arg3, 0, CDW1)
Felix Singer86bc2e72022-12-16 04:40:39 +0100[diff] [blame^]176 CDW1 |= 4
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]177 Return (Arg3)
178 }
179}