Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* Intel 82801Ix support */ |
| 18 | |
| 19 | Scope(\) |
| 20 | { |
| 21 | // IO-Trap at 0x800. This is the ACPI->SMI communication interface. |
| 22 | |
| 23 | OperationRegion(IO_T, SystemIO, 0x800, 0x10) |
| 24 | Field(IO_T, ByteAcc, NoLock, Preserve) |
| 25 | { |
| 26 | Offset(0x8), |
| 27 | TRP0, 8 // IO-Trap at 0x808 |
| 28 | } |
| 29 | |
| 30 | // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) |
| 31 | OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) |
| 32 | Field(PMIO, ByteAcc, NoLock, Preserve) |
| 33 | { |
| 34 | Offset(0x11), |
| 35 | THRO, 1, // force thermal throttling |
| 36 | Offset(0x42), // General Purpose Control |
| 37 | , 1, // skip 1 bit |
| 38 | GPEC, 1, // TCO status |
| 39 | Offset(0x64), |
| 40 | , 9, // skip 9 more bits |
| 41 | SCIS, 1 // TCO DMI status |
| 42 | } |
| 43 | |
| 44 | // FIXME: purposes of the GPIOs (comments) are probably wrong |
| 45 | // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l) |
| 46 | OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) |
| 47 | Field(GPIO, ByteAcc, NoLock, Preserve) |
| 48 | { |
| 49 | Offset(0x00), // GPIO Use Select |
| 50 | GU00, 8, |
| 51 | GU01, 8, |
| 52 | GU02, 8, |
| 53 | GU03, 8, |
| 54 | Offset(0x04), // GPIO IO Select |
| 55 | GIO0, 8, |
| 56 | GIO1, 8, |
| 57 | GIO2, 8, |
| 58 | GIO3, 8, |
| 59 | Offset(0x0c), // GPIO Level |
| 60 | GP00, 1, |
| 61 | GP01, 1, |
| 62 | GP02, 1, |
| 63 | GP03, 1, |
| 64 | GP04, 1, |
| 65 | GP05, 1, |
Stefan Tauner | 1758e73 | 2018-08-04 22:03:12 +0200 | [diff] [blame] | 66 | GP06, 1, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 67 | GP07, 1, |
| 68 | GP08, 1, |
Stefan Tauner | 1758e73 | 2018-08-04 22:03:12 +0200 | [diff] [blame] | 69 | GP09, 1, |
| 70 | GP10, 1, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 71 | GP11, 1, |
Stefan Tauner | 1758e73 | 2018-08-04 22:03:12 +0200 | [diff] [blame] | 72 | GP12, 1, |
| 73 | GP13, 1, |
| 74 | GP14, 1, |
| 75 | GP15, 1, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 76 | GP16, 1, |
| 77 | GP17, 1, |
Stefan Tauner | 1758e73 | 2018-08-04 22:03:12 +0200 | [diff] [blame] | 78 | GP18, 1, |
| 79 | GP19, 1, |
| 80 | GP20, 1, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 81 | GP21, 1, |
| 82 | GP22, 1, |
Stefan Tauner | 1758e73 | 2018-08-04 22:03:12 +0200 | [diff] [blame] | 83 | GP23, 1, |
| 84 | GP24, 1, |
| 85 | GP25, 1, |
| 86 | GP26, 1, |
| 87 | GP27, 1, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 88 | GP28, 1, |
| 89 | GP29, 1, |
| 90 | GP30, 1, |
| 91 | GP31, 1, |
| 92 | Offset(0x18), // GPIO Blink |
| 93 | GB00, 8, |
| 94 | GB01, 8, |
| 95 | GB02, 8, |
| 96 | GB03, 8, |
| 97 | Offset(0x2c), // GPIO Invert |
| 98 | GIV0, 8, |
| 99 | GIV1, 8, |
| 100 | GIV2, 8, |
| 101 | GIV3, 8, |
| 102 | Offset(0x30), // GPIO Use Select 2 |
| 103 | GU04, 8, |
| 104 | GU05, 8, |
| 105 | GU06, 8, |
| 106 | GU07, 8, |
| 107 | Offset(0x34), // GPIO IO Select 2 |
| 108 | GIO4, 8, |
| 109 | GIO5, 8, |
| 110 | GIO6, 8, |
| 111 | GIO7, 8, |
| 112 | Offset(0x38), // GPIO Level 2 |
| 113 | GP32, 1, |
Stefan Tauner | 1758e73 | 2018-08-04 22:03:12 +0200 | [diff] [blame] | 114 | GP33, 1, |
| 115 | GP34, 1, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 116 | GP35, 1, |
Stefan Tauner | 1758e73 | 2018-08-04 22:03:12 +0200 | [diff] [blame] | 117 | GP36, 1, |
| 118 | GP37, 1, |
| 119 | GP38, 1, |
| 120 | GP39, 1, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 121 | GL05, 8, |
| 122 | GL06, 8, |
| 123 | GL07, 8 |
| 124 | } |
| 125 | |
| 126 | |
| 127 | // ICH9 Root Complex Register Block. Memory Mapped through RCBA) |
| 128 | OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) |
| 129 | Field(RCRB, DWordAcc, Lock, Preserve) |
| 130 | { |
| 131 | Offset(0x0000), // Backbone |
| 132 | Offset(0x1000), // Chipset |
| 133 | Offset(0x3000), // Legacy Configuration Registers |
| 134 | Offset(0x3404), // High Performance Timer Configuration |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 135 | HPAS, 2, // Address Select |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 136 | , 5, |
| 137 | HPTE, 1, // Address Enable |
| 138 | Offset(0x3418), // FD (Function Disable) |
| 139 | , 2, // Reserved |
| 140 | SA1D, 1, // SATA disable |
| 141 | SMBD, 1, // SMBUS disable |
| 142 | HDAD, 1, // Azalia disable |
| 143 | , 2, // Reserved |
| 144 | US6D, 1, // UHCI #6 disable |
| 145 | US1D, 1, // UHCI #1 disable |
| 146 | US2D, 1, // UHCI #2 disable |
| 147 | US3D, 1, // UHCI #3 disable |
| 148 | US4D, 1, // UHCI #4 disable |
| 149 | US5D, 1, // UHCI #5 disable |
| 150 | EH2D, 1, // EHCI disable |
| 151 | LPBD, 1, // LPC bridge disable |
| 152 | EH1D, 1, // EHCI disable |
| 153 | Offset(0x341a), // FD Root Ports |
| 154 | RP1D, 1, // Root Port 1 disable |
| 155 | RP2D, 1, // Root Port 2 disable |
| 156 | RP3D, 1, // Root Port 3 disable |
| 157 | RP4D, 1, // Root Port 4 disable |
| 158 | RP5D, 1, // Root Port 5 disable |
| 159 | RP6D, 1, // Root Port 6 disable |
| 160 | , 2, // Reserved |
| 161 | THRD, 1, // Thermal Throttle disable |
| 162 | SA2D, 1, // SATA disable |
| 163 | } |
| 164 | |
| 165 | } |
| 166 | |
| 167 | // 0:1b.0 High Definition Audio (Azalia) |
| 168 | #include "audio.asl" |
| 169 | |
| 170 | // PCI Express Ports |
Arthur Heymans | dff185a | 2018-12-30 12:59:39 +0100 | [diff] [blame^] | 171 | #include <southbridge/intel/common/acpi/pcie.asl> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 172 | |
| 173 | // USB |
| 174 | #include "usb.asl" |
| 175 | |
| 176 | // PCI Bridge |
| 177 | #include "pci.asl" |
| 178 | |
| 179 | // LPC Bridge |
| 180 | #include "lpc.asl" |
| 181 | |
| 182 | // SATA |
| 183 | #include "sata.asl" |
| 184 | |
| 185 | // SMBus |
| 186 | #include "smbus.asl" |
| 187 | |
| 188 | Method (_OSC, 4) |
| 189 | { |
| 190 | /* Check for proper GUID */ |
| 191 | If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 192 | { |
| 193 | /* Let OS control everything */ |
| 194 | Return (Arg3) |
| 195 | } |
| 196 | Else |
| 197 | { |
| 198 | /* Unrecognized UUID */ |
| 199 | CreateDWordField (Arg3, 0, CDW1) |
| 200 | Or (CDW1, 4, CDW1) |
| 201 | Return (Arg3) |
| 202 | } |
| 203 | } |