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review.coreboot.org / coreboot / 182dbdeac4b2489f8d03a47a79ab28ad556d9d21 / . / src / southbridge / intel / i82801ix / acpi / ich9.asl
blob: 2075326d46a7225bf5941e48b6ccffcf3056c186 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]3
4/* Intel 82801Ix support */
5
6Scope(\)
7{
8 // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
9
10 OperationRegion(IO_T, SystemIO, 0x800, 0x10)
11 Field(IO_T, ByteAcc, NoLock, Preserve)
12 {
13 Offset(0x8),
14 TRP0, 8 // IO-Trap at 0x808
15 }
16
17 // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
18 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
19 Field(PMIO, ByteAcc, NoLock, Preserve)
20 {
21 Offset(0x11),
22 THRO, 1, // force thermal throttling
23 Offset(0x42), // General Purpose Control
24 , 1, // skip 1 bit
25 GPEC, 1, // TCO status
26 Offset(0x64),
27 , 9, // skip 9 more bits
28 SCIS, 1 // TCO DMI status
29 }
30
31 // FIXME: purposes of the GPIOs (comments) are probably wrong
32 // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
33 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
34 Field(GPIO, ByteAcc, NoLock, Preserve)
35 {
36 Offset(0x00), // GPIO Use Select
37 GU00, 8,
38 GU01, 8,
39 GU02, 8,
40 GU03, 8,
41 Offset(0x04), // GPIO IO Select
42 GIO0, 8,
43 GIO1, 8,
44 GIO2, 8,
45 GIO3, 8,
46 Offset(0x0c), // GPIO Level
47 GP00, 1,
48 GP01, 1,
49 GP02, 1,
50 GP03, 1,
51 GP04, 1,
52 GP05, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]53 GP06, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]54 GP07, 1,
55 GP08, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]56 GP09, 1,
57 GP10, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]58 GP11, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]59 GP12, 1,
60 GP13, 1,
61 GP14, 1,
62 GP15, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]63 GP16, 1,
64 GP17, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]65 GP18, 1,
66 GP19, 1,
67 GP20, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]68 GP21, 1,
69 GP22, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]70 GP23, 1,
71 GP24, 1,
72 GP25, 1,
73 GP26, 1,
74 GP27, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]75 GP28, 1,
76 GP29, 1,
77 GP30, 1,
78 GP31, 1,
79 Offset(0x18), // GPIO Blink
80 GB00, 8,
81 GB01, 8,
82 GB02, 8,
83 GB03, 8,
84 Offset(0x2c), // GPIO Invert
85 GIV0, 8,
86 GIV1, 8,
87 GIV2, 8,
88 GIV3, 8,
89 Offset(0x30), // GPIO Use Select 2
90 GU04, 8,
91 GU05, 8,
92 GU06, 8,
93 GU07, 8,
94 Offset(0x34), // GPIO IO Select 2
95 GIO4, 8,
96 GIO5, 8,
97 GIO6, 8,
98 GIO7, 8,
99 Offset(0x38), // GPIO Level 2
100 GP32, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]101 GP33, 1,
102 GP34, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]103 GP35, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]104 GP36, 1,
105 GP37, 1,
106 GP38, 1,
107 GP39, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]108 GL05, 8,
109 GL06, 8,
110 GL07, 8
111 }
112
113
114 // ICH9 Root Complex Register Block. Memory Mapped through RCBA)
115 OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
116 Field(RCRB, DWordAcc, Lock, Preserve)
117 {
118 Offset(0x0000), // Backbone
119 Offset(0x1000), // Chipset
120 Offset(0x3000), // Legacy Configuration Registers
121 Offset(0x3404), // High Performance Timer Configuration
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200[diff] [blame]122 HPAS, 2, // Address Select
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]123 , 5,
124 HPTE, 1, // Address Enable
125 Offset(0x3418), // FD (Function Disable)
126 , 2, // Reserved
127 SA1D, 1, // SATA disable
128 SMBD, 1, // SMBUS disable
129 HDAD, 1, // Azalia disable
130 , 2, // Reserved
131 US6D, 1, // UHCI #6 disable
132 US1D, 1, // UHCI #1 disable
133 US2D, 1, // UHCI #2 disable
134 US3D, 1, // UHCI #3 disable
135 US4D, 1, // UHCI #4 disable
136 US5D, 1, // UHCI #5 disable
137 EH2D, 1, // EHCI disable
138 LPBD, 1, // LPC bridge disable
139 EH1D, 1, // EHCI disable
140 Offset(0x341a), // FD Root Ports
141 RP1D, 1, // Root Port 1 disable
142 RP2D, 1, // Root Port 2 disable
143 RP3D, 1, // Root Port 3 disable
144 RP4D, 1, // Root Port 4 disable
145 RP5D, 1, // Root Port 5 disable
146 RP6D, 1, // Root Port 6 disable
147 , 2, // Reserved
148 THRD, 1, // Thermal Throttle disable
149 SA2D, 1, // SATA disable
150 }
151
152}
153
154// 0:1b.0 High Definition Audio (Azalia)
155#include "audio.asl"
156
157// PCI Express Ports
Arthur Heymansdff185a2018-12-30 12:59:39 +0100[diff] [blame]158#include <southbridge/intel/common/acpi/pcie.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]159
160// USB
161#include "usb.asl"
162
163// PCI Bridge
164#include "pci.asl"
165
166// LPC Bridge
167#include "lpc.asl"
168
169// SATA
170#include "sata.asl"
171
172// SMBus
Elyes HAOUAS085ab5a2019-10-31 10:12:02 +0100[diff] [blame]173#include <southbridge/intel/common/acpi/smbus.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]174
175Method (_OSC, 4)
176{
177 /* Check for proper GUID */
178 If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
179 {
180 /* Let OS control everything */
181 Return (Arg3)
182 }
183 Else
184 {
185 /* Unrecognized UUID */
186 CreateDWordField (Arg3, 0, CDW1)
187 Or (CDW1, 4, CDW1)
188 Return (Arg3)
189 }
190}