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review.coreboot.org / coreboot / e72a8a3047c535bda03aecce2eca134608d1a93c / . / src / southbridge / intel / i82801ix / acpi / ich9.asl
blob: 8ded41324608af15fae4424b287c3b2dfbef7a62 [file] [log] [blame]
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
22/* Intel 82801Ix support */
23
24Scope(\)
25{
26 // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
27
28 OperationRegion(IO_T, SystemIO, 0x800, 0x10)
29 Field(IO_T, ByteAcc, NoLock, Preserve)
30 {
31 Offset(0x8),
32 TRP0, 8 // IO-Trap at 0x808
33 }
34
35 // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
36 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
37 Field(PMIO, ByteAcc, NoLock, Preserve)
38 {
39 Offset(0x11),
40 THRO, 1, // force thermal throttling
41 Offset(0x42), // General Purpose Control
42 , 1, // skip 1 bit
43 GPEC, 1, // TCO status
44 Offset(0x64),
45 , 9, // skip 9 more bits
46 SCIS, 1 // TCO DMI status
47 }
48
49 // FIXME: purposes of the GPIOs (comments) are probably wrong
50 // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
51 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
52 Field(GPIO, ByteAcc, NoLock, Preserve)
53 {
54 Offset(0x00), // GPIO Use Select
55 GU00, 8,
56 GU01, 8,
57 GU02, 8,
58 GU03, 8,
59 Offset(0x04), // GPIO IO Select
60 GIO0, 8,
61 GIO1, 8,
62 GIO2, 8,
63 GIO3, 8,
64 Offset(0x0c), // GPIO Level
65 GP00, 1,
66 GP01, 1,
67 GP02, 1,
68 GP03, 1,
69 GP04, 1,
70 GP05, 1,
71 GP06, 1, // GDET
72 GP07, 1,
73 GP08, 1,
74 GP09, 1, // HPMU
75 GP10, 1, // GPSE
76 GP11, 1,
77 GP12, 1, // WLED
78 GP13, 1, // BLED
79 GP14, 1, // GLED
80 GP15, 1, // GDIS
81 GP16, 1,
82 GP17, 1,
83 GP18, 1, // SPCI
84 GP19, 1, // TSDT
85 GP20, 1, // SCPU
86 GP21, 1,
87 GP22, 1,
88 GP23, 1, // LANP
89 GP24, 1, // DKLR
90 GP25, 1, // WLAN
91 GP26, 1, // SATA_PWR_EN #0 / SPOF
92 GP27, 1, // SATA_PWR_EN #1 / SPMU
93 GP28, 1,
94 GP29, 1,
95 GP30, 1,
96 GP31, 1,
97 Offset(0x18), // GPIO Blink
98 GB00, 8,
99 GB01, 8,
100 GB02, 8,
101 GB03, 8,
102 Offset(0x2c), // GPIO Invert
103 GIV0, 8,
104 GIV1, 8,
105 GIV2, 8,
106 GIV3, 8,
107 Offset(0x30), // GPIO Use Select 2
108 GU04, 8,
109 GU05, 8,
110 GU06, 8,
111 GU07, 8,
112 Offset(0x34), // GPIO IO Select 2
113 GIO4, 8,
114 GIO5, 8,
115 GIO6, 8,
116 GIO7, 8,
117 Offset(0x38), // GPIO Level 2
118 GP32, 1,
119 GP33, 1, // CREN
120 GP34, 1, // CRRS
121 GP35, 1,
122 GP36, 1, // STAD
123 GP37, 1, // PATA_PWR_EN / HDDE
124 GP38, 1, // Battery / Power (?) / MB00
125 GP39, 1, // ?? / MB01
126 GL05, 8,
127 GL06, 8,
128 GL07, 8
129 }
130
131
132 // ICH9 Root Complex Register Block. Memory Mapped through RCBA)
133 OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
134 Field(RCRB, DWordAcc, Lock, Preserve)
135 {
136 Offset(0x0000), // Backbone
137 Offset(0x1000), // Chipset
138 Offset(0x3000), // Legacy Configuration Registers
139 Offset(0x3404), // High Performance Timer Configuration
140 HPAS, 2, // Address Select
141 , 5,
142 HPTE, 1, // Address Enable
143 Offset(0x3418), // FD (Function Disable)
144 , 2, // Reserved
145 SA1D, 1, // SATA disable
146 SMBD, 1, // SMBUS disable
147 HDAD, 1, // Azalia disable
148 , 2, // Reserved
149 US6D, 1, // UHCI #6 disable
150 US1D, 1, // UHCI #1 disable
151 US2D, 1, // UHCI #2 disable
152 US3D, 1, // UHCI #3 disable
153 US4D, 1, // UHCI #4 disable
154 US5D, 1, // UHCI #5 disable
155 EH2D, 1, // EHCI disable
156 LPBD, 1, // LPC bridge disable
157 EH1D, 1, // EHCI disable
158 Offset(0x341a), // FD Root Ports
159 RP1D, 1, // Root Port 1 disable
160 RP2D, 1, // Root Port 2 disable
161 RP3D, 1, // Root Port 3 disable
162 RP4D, 1, // Root Port 4 disable
163 RP5D, 1, // Root Port 5 disable
164 RP6D, 1, // Root Port 6 disable
165 , 2, // Reserved
166 THRD, 1, // Thermal Throttle disable
167 SA2D, 1, // SATA disable
168 }
169
170}
171
172// 0:1b.0 High Definition Audio (Azalia)
173#include "audio.asl"
174
175// PCI Express Ports
176#include "pcie.asl"
177
178// USB
179#include "usb.asl"
180
181// PCI Bridge
182#include "pci.asl"
183
184// LPC Bridge
185#include "lpc.asl"
186
187// SATA
188#include "sata.asl"
189
190// SMBus
191#include "smbus.asl"
192
193Method (_OSC, 4)
194{
195 /* Check for proper GUID */
196 If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
197 {
198 /* Let OS control everything */
199 Return (Arg3)
200 }
201 Else
202 {
203 /* Unrecognized UUID */
204 CreateDWordField (Arg3, 0, CDW1)
205 Or (CDW1, 4, CDW1)
206 Return (Arg3)
207 }
208}