Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 5 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 6 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 9 | #include <northbridge/intel/sandybridge/chip.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <delay.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 12 | #include <types.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 13 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 14 | #include "raminit_native.h" |
| 15 | #include "raminit_common.h" |
Angel Pons | 7f6586f | 2020-03-21 12:45:12 +0100 | [diff] [blame] | 16 | #include "raminit_tables.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 17 | #include "sandybridge.h" |
| 18 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 19 | /* FIXME: no support for 3-channel chipsets */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 20 | |
| 21 | static void sfence(void) |
| 22 | { |
| 23 | asm volatile ("sfence"); |
| 24 | } |
| 25 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 26 | /* Toggle IO reset bit */ |
| 27 | static void toggle_io_reset(void) |
| 28 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 29 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 30 | MCHBAR32(MC_INIT_STATE_G) = r32 | (1 << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 31 | udelay(1); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 32 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~(1 << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 33 | udelay(1); |
| 34 | } |
| 35 | |
| 36 | static u32 get_XOVER_CLK(u8 rankmap) |
| 37 | { |
| 38 | return rankmap << 24; |
| 39 | } |
| 40 | |
| 41 | static u32 get_XOVER_CMD(u8 rankmap) |
| 42 | { |
| 43 | u32 reg; |
| 44 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 45 | /* Enable xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 46 | reg = 0x4000; |
| 47 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 48 | /* Enable xover ctl */ |
| 49 | if (rankmap & 0x03) |
| 50 | reg |= (1 << 17); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 51 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 52 | if (rankmap & 0x0c) |
| 53 | reg |= (1 << 26); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 54 | |
| 55 | return reg; |
| 56 | } |
| 57 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 58 | void dram_find_common_params(ramctr_timing *ctrl) |
| 59 | { |
| 60 | size_t valid_dimms; |
| 61 | int channel, slot; |
| 62 | dimm_info *dimms = &ctrl->info; |
| 63 | |
| 64 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 65 | valid_dimms = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 66 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 67 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 68 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 69 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 70 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 71 | continue; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 72 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 73 | valid_dimms++; |
| 74 | |
| 75 | /* Find all possible CAS combinations */ |
| 76 | ctrl->cas_supported &= dimm->cas_supported; |
| 77 | |
| 78 | /* Find the smallest common latencies supported by all DIMMs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 79 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 80 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 81 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 82 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 83 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 84 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 85 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 86 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 87 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 88 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 89 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 90 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 91 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | if (!ctrl->cas_supported) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 95 | die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); |
| 96 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 97 | if (!valid_dimms) |
| 98 | die("No valid DIMMs found"); |
| 99 | } |
| 100 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 101 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 102 | { |
| 103 | u32 reg; |
| 104 | int channel; |
| 105 | |
| 106 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 107 | /* Enable xover clk */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 108 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 109 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 110 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 111 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 112 | /* Enable xover ctl & xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 113 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 114 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 115 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 116 | } |
| 117 | } |
| 118 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 119 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 120 | { |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 121 | u32 addr, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 122 | |
| 123 | stretch = ctrl->ref_card_offset[channel]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 124 | /* |
| 125 | * ODT stretch: |
| 126 | * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. |
| 127 | */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 128 | if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 129 | if (stretch == 2) |
| 130 | stretch = 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 131 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 132 | addr = SCHED_SECOND_CBIT_ch(channel); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 133 | MCHBAR32_AND_OR(addr, ~(0xf << 10), (stretch << 12) | (stretch << 10)); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 134 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 135 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 136 | addr = TC_OTHP_ch(channel); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 137 | MCHBAR32_AND_OR(addr, ~(0xf << 16), (stretch << 16) | (stretch << 18)); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 138 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 139 | } |
| 140 | } |
| 141 | |
| 142 | void dram_timing_regs(ramctr_timing *ctrl) |
| 143 | { |
| 144 | u32 reg, addr, val32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 145 | int channel; |
| 146 | |
| 147 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 148 | /* BIN parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 149 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 150 | reg |= (ctrl->tRCD << 0); |
| 151 | reg |= (ctrl->tRP << 4); |
| 152 | reg |= (ctrl->CAS << 8); |
| 153 | reg |= (ctrl->CWL << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 154 | reg |= (ctrl->tRAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 155 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); |
| 156 | MCHBAR32(TC_DBP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 157 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 158 | /* Regular access parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 159 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 160 | reg |= (ctrl->tRRD << 0); |
| 161 | reg |= (ctrl->tRTP << 4); |
| 162 | reg |= (ctrl->tCKE << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 163 | reg |= (ctrl->tWTR << 12); |
| 164 | reg |= (ctrl->tFAW << 16); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 165 | reg |= (ctrl->tWR << 24); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 166 | reg |= (3 << 30); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 167 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); |
| 168 | MCHBAR32(TC_RAP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 169 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 170 | /* Other parameters */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 171 | addr = TC_OTHP_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 172 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 173 | reg |= (ctrl->tXPDLL << 0); |
| 174 | reg |= (ctrl->tXP << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 175 | reg |= (ctrl->tAONPD << 8); |
| 176 | reg |= 0xa0000; |
| 177 | printram("OTHP [%x] = %x\n", addr, reg); |
| 178 | MCHBAR32(addr) = reg; |
| 179 | |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 180 | /* Debug parameters - only applies to Ivy Bridge */ |
| 181 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 182 | reg = 0; |
| 183 | |
| 184 | /* |
| 185 | * If tXP and tXPDLL are very high, we need to increase them by one. |
| 186 | * This can only happen on Ivy Bridge, and when overclocking the RAM. |
| 187 | */ |
| 188 | if (ctrl->tXP >= 8) |
| 189 | reg |= (1 << 12); |
| 190 | |
| 191 | if (ctrl->tXPDLL >= 32) |
| 192 | reg |= (1 << 13); |
| 193 | |
| 194 | MCHBAR32(TC_DTP_ch(channel)) = reg; |
| 195 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 196 | |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 197 | MCHBAR32_OR(addr, 0x00020000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 198 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 199 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 200 | |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 201 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 202 | * TC-Refresh timing parameters: |
| 203 | * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow |
| 204 | * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 205 | */ |
| 206 | val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
| 207 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 208 | reg = ((ctrl->tREFI & 0xffff) << 0) | |
| 209 | ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); |
| 210 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 211 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); |
| 212 | MCHBAR32(TC_RFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 213 | |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 214 | MCHBAR32_OR(TC_RFP_ch(channel), 0xff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 215 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 216 | /* Self-refresh timing parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 217 | reg = 0; |
| 218 | val32 = tDLLK; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 219 | reg = (reg & ~0x00000fff) | (val32 << 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 220 | val32 = ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 221 | reg = (reg & ~0x0000f000) | (val32 << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 222 | val32 = tDLLK - ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 223 | reg = (reg & ~0x03ff0000) | (val32 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 224 | val32 = ctrl->tMOD - 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 225 | reg = (reg & ~0xf0000000) | (val32 << 28); |
| 226 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 227 | MCHBAR32(TC_SRFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 228 | } |
| 229 | } |
| 230 | |
| 231 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 232 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 233 | int channel; |
| 234 | dimm_info *info = &ctrl->info; |
| 235 | |
| 236 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 237 | dimm_attr *dimmA, *dimmB; |
| 238 | u32 reg = 0; |
| 239 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 240 | if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 241 | dimmA = &info->dimm[channel][0]; |
| 242 | dimmB = &info->dimm[channel][1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 243 | reg |= (0 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 244 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 245 | dimmA = &info->dimm[channel][1]; |
| 246 | dimmB = &info->dimm[channel][0]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 247 | reg |= (1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 248 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 249 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 250 | if (dimmA && (dimmA->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 251 | reg |= (dimmA->size_mb / 256) << 0; |
| 252 | reg |= (dimmA->ranks - 1) << 17; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 253 | reg |= (dimmA->width / 8 - 1) << 19; |
| 254 | } |
| 255 | |
| 256 | if (dimmB && (dimmB->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 257 | reg |= (dimmB->size_mb / 256) << 8; |
| 258 | reg |= (dimmB->ranks - 1) << 18; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 259 | reg |= (dimmB->width / 8 - 1) << 20; |
| 260 | } |
| 261 | |
Patrick Rudolph | 4e0cd82 | 2020-05-01 18:35:36 +0200 | [diff] [blame] | 262 | /* |
| 263 | * Rank interleave: Bit 16 of the physical address space sets |
| 264 | * the rank to use in a dual single rank DIMM configuration. |
| 265 | * That results in every 64KiB being interleaved between two ranks. |
| 266 | */ |
| 267 | reg |= 1 << 21; |
| 268 | /* Enhanced interleave */ |
| 269 | reg |= 1 << 22; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 270 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 271 | if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 272 | ctrl->mad_dimm[channel] = reg; |
| 273 | } else { |
| 274 | ctrl->mad_dimm[channel] = 0; |
| 275 | } |
| 276 | } |
| 277 | } |
| 278 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 279 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 280 | { |
| 281 | int channel; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 282 | u32 ecc; |
| 283 | |
| 284 | if (ctrl->ecc_enabled) |
| 285 | ecc = training ? (1 << 24) : (3 << 24); |
| 286 | else |
| 287 | ecc = 0; |
| 288 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 289 | FOR_ALL_CHANNELS { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 290 | MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 291 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 292 | |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 293 | if (ctrl->ecc_enabled) |
| 294 | udelay(10); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 295 | } |
| 296 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 297 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 298 | { |
| 299 | u32 reg, ch0size, ch1size; |
| 300 | u8 val; |
| 301 | reg = 0; |
| 302 | val = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 303 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 304 | if (training) { |
| 305 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 306 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 307 | } else { |
| 308 | ch0size = ctrl->channel_size_mb[0]; |
| 309 | ch1size = ctrl->channel_size_mb[1]; |
| 310 | } |
| 311 | |
| 312 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 313 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 314 | val = ch1size / 256; |
| 315 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 316 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 317 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 318 | MCHBAR32(MAD_CHNL) = 0x24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 319 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 320 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 321 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 322 | val = ch0size / 256; |
| 323 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 324 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 325 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 326 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 327 | } |
| 328 | } |
| 329 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 330 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 331 | |
| 332 | static unsigned int get_mmio_size(void) |
| 333 | { |
| 334 | const struct device *dev; |
| 335 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 336 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 337 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 338 | if (dev) |
| 339 | cfg = dev->chip_info; |
| 340 | |
| 341 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 342 | if (!cfg || cfg->pci_mmio_size == 0) |
| 343 | return DEFAULT_PCI_MMIO_SIZE; |
| 344 | else |
| 345 | return cfg->pci_mmio_size; |
| 346 | } |
| 347 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 348 | /* |
| 349 | * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. |
| 350 | * The ME/PCU/.. has the ability to change this. |
| 351 | * Return 0: ECC is optional |
| 352 | * Return 1: ECC is forced |
| 353 | */ |
| 354 | bool get_host_ecc_forced(void) |
| 355 | { |
| 356 | /* read Capabilities A Register */ |
| 357 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 358 | return !!(reg32 & (1 << 24)); |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * Returns the ECC capability. |
| 363 | * The ME/PCU/.. has the ability to change this. |
| 364 | * Return 0: ECC is disabled |
| 365 | * Return 1: ECC is possible |
| 366 | */ |
| 367 | bool get_host_ecc_cap(void) |
| 368 | { |
| 369 | /* read Capabilities A Register */ |
| 370 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 371 | return !(reg32 & (1 << 25)); |
| 372 | } |
| 373 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 374 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 375 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 376 | u32 reg, val, reclaim, tom, gfxstolen, gttsize; |
| 377 | size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; |
| 378 | size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 379 | uint16_t ggc; |
| 380 | |
| 381 | mmiosize = get_mmio_size(); |
| 382 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 383 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 384 | if (!(ggc & 2)) { |
| 385 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 386 | gttsize = ((ggc >> 8) & 0x3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 387 | } else { |
| 388 | gfxstolen = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 389 | gttsize = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 390 | } |
| 391 | |
| 392 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 393 | |
| 394 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 395 | |
| 396 | mestolenbase = tom - me_uma_size; |
| 397 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 398 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); |
| 399 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 400 | gfxstolenbase = toludbase - gfxstolen; |
| 401 | gttbase = gfxstolenbase - gttsize; |
| 402 | |
| 403 | tsegbase = gttbase - tsegsize; |
| 404 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 405 | /* Round tsegbase down to nearest address aligned to tsegsize */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 406 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 407 | tsegbase &= ~(tsegsize - 1); |
| 408 | |
| 409 | gttbase -= tsegbasedelta; |
| 410 | gfxstolenbase -= tsegbasedelta; |
| 411 | toludbase -= tsegbasedelta; |
| 412 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 413 | /* Test if it is possible to reclaim a hole in the RAM addressing */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 414 | if (tom - me_uma_size > toludbase) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 415 | /* Reclaim is possible */ |
| 416 | reclaim = 1; |
| 417 | remapbase = MAX(4096, tom - me_uma_size); |
| 418 | remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 419 | touudbase = remaplimit + 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 420 | } else { |
| 421 | // Reclaim not possible |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 422 | reclaim = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 423 | touudbase = tom - me_uma_size; |
| 424 | } |
| 425 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 426 | /* Update memory map in PCIe configuration space */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 427 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 428 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 429 | /* TOM (top of memory) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 430 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 431 | val = tom & 0xfff; |
| 432 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 433 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 434 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 435 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 436 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 437 | val = tom & 0xfffff000; |
| 438 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 439 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 440 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 441 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 442 | /* TOLUD (Top Of Low Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 443 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 444 | val = toludbase & 0xfff; |
| 445 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 446 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 447 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 448 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 449 | /* TOUUD LSB (Top Of Upper Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 450 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 451 | val = touudbase & 0xfff; |
| 452 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 453 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 454 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 455 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 456 | /* TOUUD MSB */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 457 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 458 | val = touudbase & 0xfffff000; |
| 459 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 460 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 461 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 462 | |
| 463 | if (reclaim) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 464 | /* REMAP BASE */ |
| 465 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 466 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 467 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 468 | /* REMAP LIMIT */ |
| 469 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 470 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 471 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 472 | /* TSEG */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 473 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 474 | val = tsegbase & 0xfff; |
| 475 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 476 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 477 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 478 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 479 | /* GFX stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 480 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 481 | val = gfxstolenbase & 0xfff; |
| 482 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 483 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 484 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 485 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 486 | /* GTT stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 487 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 488 | val = gttbase & 0xfff; |
| 489 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 490 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 491 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 492 | |
| 493 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 494 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 495 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 496 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 497 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 498 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 499 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 500 | /* ME base */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 501 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 502 | val = mestolenbase & 0xfff; |
| 503 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 504 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 505 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 506 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 507 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 508 | val = mestolenbase & 0xfffff000; |
| 509 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 510 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 511 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 512 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 513 | /* ME mask */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 514 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 515 | val = (0x80000 - me_uma_size) & 0xfff; |
| 516 | reg = (reg & ~0xfff00000) | (val << 20); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 517 | reg = reg | ME_STLEN_EN; /* Set ME memory enable */ |
| 518 | reg = reg | MELCK; /* Set lock bit on ME mem */ |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 519 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 520 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 521 | } |
| 522 | } |
| 523 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 524 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 525 | { |
| 526 | int channel, slotrank; |
| 527 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 528 | /* Choose a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 529 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 530 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 531 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 532 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 533 | /* Choose a populated rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 534 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 535 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 536 | iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 537 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 538 | /* |
| 539 | * Execute command queue - why is bit 22 set here?! |
| 540 | * |
| 541 | * This is actually using the IOSAV state machine as a timer, so refresh is allowed. |
| 542 | */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 543 | iosav_run_queue(channel, 1, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 544 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 545 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 546 | } |
| 547 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 548 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 549 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 550 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 551 | int channel; |
| 552 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 553 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 554 | ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 555 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 556 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 557 | } while ((reg & 0x14) == 0); |
| 558 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 559 | /* Set state of memory controller */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 560 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 561 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 562 | MCHBAR32(MC_INIT_STATE) = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 563 | reg |= 2; /* DDR reset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 564 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 565 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 566 | /* Assert DIMM reset signal */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 567 | MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 1)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 568 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 569 | /* Wait 200us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 570 | udelay(200); |
| 571 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 572 | /* Deassert DIMM reset signal */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 573 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 574 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 575 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 576 | udelay(500); |
| 577 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 578 | /* Enable DCLK */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 579 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 580 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 581 | /* XXX Wait 20ns */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 582 | udelay(1); |
| 583 | |
| 584 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 585 | /* Set valid rank CKE */ |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 586 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 587 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 588 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 589 | /* Wait 10ns for ranks to settle */ |
| 590 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 591 | |
| 592 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 593 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 594 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 595 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 596 | write_reset(ctrl); |
| 597 | } |
| 598 | } |
| 599 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 600 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 601 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 602 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 603 | |
| 604 | if (ctrl->rank_mirror[channel][slotrank]) { |
| 605 | /* DDR3 Rank1 Address mirror |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 606 | swap the following pins: |
| 607 | A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 608 | reg = ((reg >> 1) & 1) | ((reg << 1) & 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 609 | val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 610 | } |
| 611 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 612 | const struct iosav_ssq sequence[] = { |
| 613 | /* DRAM command MRS */ |
| 614 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 615 | .sp_cmd_ctrl = { |
| 616 | .command = IOSAV_MRS, |
| 617 | }, |
| 618 | .subseq_ctrl = { |
| 619 | .cmd_executions = 1, |
| 620 | .cmd_delay_gap = 4, |
| 621 | .post_ssq_wait = 4, |
| 622 | .data_direction = SSQ_NA, |
| 623 | }, |
| 624 | .sp_cmd_addr = { |
| 625 | .address = val, |
| 626 | .rowbits = 6, |
| 627 | .bank = reg, |
| 628 | .rank = slotrank, |
| 629 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 630 | }, |
| 631 | /* DRAM command MRS */ |
| 632 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 633 | .sp_cmd_ctrl = { |
| 634 | .command = IOSAV_MRS, |
| 635 | .ranksel_ap = 1, |
| 636 | }, |
| 637 | .subseq_ctrl = { |
| 638 | .cmd_executions = 1, |
| 639 | .cmd_delay_gap = 4, |
| 640 | .post_ssq_wait = 4, |
| 641 | .data_direction = SSQ_NA, |
| 642 | }, |
| 643 | .sp_cmd_addr = { |
| 644 | .address = val, |
| 645 | .rowbits = 6, |
| 646 | .bank = reg, |
| 647 | .rank = slotrank, |
| 648 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 649 | }, |
| 650 | /* DRAM command MRS */ |
| 651 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 652 | .sp_cmd_ctrl = { |
| 653 | .command = IOSAV_MRS, |
| 654 | }, |
| 655 | .subseq_ctrl = { |
| 656 | .cmd_executions = 1, |
| 657 | .cmd_delay_gap = 4, |
| 658 | .post_ssq_wait = ctrl->tMOD, |
| 659 | .data_direction = SSQ_NA, |
| 660 | }, |
| 661 | .sp_cmd_addr = { |
| 662 | .address = val, |
| 663 | .rowbits = 6, |
| 664 | .bank = reg, |
| 665 | .rank = slotrank, |
| 666 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 667 | }, |
| 668 | }; |
| 669 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 670 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 671 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 672 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 673 | } |
| 674 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 675 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 676 | { |
| 677 | u16 mr0reg, mch_cas, mch_wr; |
| 678 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 679 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 680 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 681 | /* Convert CAS to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 682 | if (ctrl->CAS < 12) { |
| 683 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 684 | } else { |
| 685 | mch_cas = (u16) (ctrl->CAS - 12); |
| 686 | mch_cas = ((mch_cas << 1) | 0x1); |
| 687 | } |
| 688 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 689 | /* Convert tWR to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 690 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 691 | |
Angel Pons | 2bf28ed | 2020-11-12 13:49:59 +0100 | [diff] [blame] | 692 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 693 | mr0reg = 1 << 8; |
| 694 | |
| 695 | mr0reg |= (mch_cas & 0x1) << 2; |
| 696 | mr0reg |= (mch_cas & 0xe) << 3; |
| 697 | mr0reg |= mch_wr << 9; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 698 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 699 | /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ |
Angel Pons | 2bf28ed | 2020-11-12 13:49:59 +0100 | [diff] [blame] | 700 | mr0reg |= !is_mobile << 12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 701 | return mr0reg; |
| 702 | } |
| 703 | |
| 704 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 705 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 706 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 707 | } |
| 708 | |
Angel Pons | f999748 | 2020-11-12 16:02:52 +0100 | [diff] [blame] | 709 | static odtmap get_ODT(ramctr_timing *ctrl, int channel) |
Angel Pons | 1a9b5aa | 2020-11-12 13:51:46 +0100 | [diff] [blame] | 710 | { |
| 711 | /* Get ODT based on rankmap */ |
| 712 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); |
| 713 | |
| 714 | if (dimms_per_ch == 1) { |
| 715 | return (const odtmap){60, 60}; |
| 716 | } else { |
| 717 | return (const odtmap){120, 30}; |
| 718 | } |
| 719 | } |
| 720 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 721 | static u32 encode_odt(u32 odt) |
| 722 | { |
| 723 | switch (odt) { |
| 724 | case 30: |
| 725 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 726 | case 60: |
| 727 | return (1 << 2); // RZQ/4 |
| 728 | case 120: |
| 729 | return (1 << 6); // RZQ/2 |
| 730 | default: |
| 731 | case 0: |
| 732 | return 0; |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 737 | { |
| 738 | odtmap odt; |
| 739 | u32 mr1reg; |
| 740 | |
Angel Pons | f999748 | 2020-11-12 16:02:52 +0100 | [diff] [blame] | 741 | odt = get_ODT(ctrl, channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 742 | mr1reg = 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 743 | |
| 744 | mr1reg |= encode_odt(odt.rttnom); |
| 745 | |
| 746 | return mr1reg; |
| 747 | } |
| 748 | |
| 749 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 750 | { |
| 751 | u16 mr1reg; |
| 752 | |
| 753 | mr1reg = make_mr1(ctrl, rank, channel); |
| 754 | |
| 755 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 756 | } |
| 757 | |
| 758 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 759 | { |
| 760 | u16 pasr, cwl, mr2reg; |
| 761 | odtmap odt; |
Angel Pons | dca3cb5 | 2020-11-13 13:42:07 +0100 | [diff] [blame^] | 762 | int srt = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 763 | |
| 764 | pasr = 0; |
| 765 | cwl = ctrl->CWL - 5; |
Angel Pons | f999748 | 2020-11-12 16:02:52 +0100 | [diff] [blame] | 766 | odt = get_ODT(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 767 | |
Angel Pons | dca3cb5 | 2020-11-13 13:42:07 +0100 | [diff] [blame^] | 768 | if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) |
| 769 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 770 | |
| 771 | mr2reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 772 | mr2reg = (mr2reg & ~0x07) | pasr; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 773 | mr2reg = (mr2reg & ~0x38) | (cwl << 3); |
| 774 | mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); |
| 775 | mr2reg = (mr2reg & ~0x80) | (srt << 7); |
| 776 | mr2reg |= (odt.rttwr / 60) << 9; |
| 777 | |
| 778 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
Angel Pons | 7f1363d | 2020-11-13 13:31:58 +0100 | [diff] [blame] | 779 | |
| 780 | /* Program MR2 shadow */ |
| 781 | u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); |
| 782 | |
| 783 | reg32 &= 3 << 14 | 3 << 6; |
| 784 | |
| 785 | reg32 |= mr2reg & ~(3 << 6); |
| 786 | |
| 787 | if (rank & 1) { |
| 788 | if (srt) |
| 789 | reg32 |= 1 << (rank / 2 + 6); |
| 790 | } else { |
| 791 | if (ctrl->rank_mirror[channel][rank]) |
| 792 | reg32 |= 1 << (rank / 2 + 14); |
| 793 | } |
| 794 | MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 795 | } |
| 796 | |
| 797 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 798 | { |
| 799 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 800 | } |
| 801 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 802 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 803 | { |
| 804 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 805 | int channel; |
| 806 | |
| 807 | FOR_ALL_POPULATED_CHANNELS { |
| 808 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 809 | /* MR2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 810 | dram_mr2(ctrl, slotrank, channel); |
| 811 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 812 | /* MR3 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 813 | dram_mr3(ctrl, slotrank, channel); |
| 814 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 815 | /* MR1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 816 | dram_mr1(ctrl, slotrank, channel); |
| 817 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 818 | /* MR0 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 819 | dram_mr0(ctrl, slotrank, channel); |
| 820 | } |
| 821 | } |
| 822 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 823 | const struct iosav_ssq zqcl_sequence[] = { |
| 824 | /* DRAM command NOP (without ODT nor chip selects) */ |
| 825 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 826 | .sp_cmd_ctrl = { |
| 827 | .command = IOSAV_NOP & ~(0xff << 8), |
| 828 | }, |
| 829 | .subseq_ctrl = { |
| 830 | .cmd_executions = 1, |
| 831 | .cmd_delay_gap = 4, |
| 832 | .post_ssq_wait = 15, |
| 833 | .data_direction = SSQ_NA, |
| 834 | }, |
| 835 | .sp_cmd_addr = { |
| 836 | .address = 2, |
| 837 | .rowbits = 6, |
| 838 | .bank = 0, |
| 839 | .rank = 0, |
| 840 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 841 | }, |
| 842 | /* DRAM command ZQCL */ |
| 843 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 844 | .sp_cmd_ctrl = { |
| 845 | .command = IOSAV_ZQCS, |
| 846 | .ranksel_ap = 1, |
| 847 | }, |
| 848 | .subseq_ctrl = { |
| 849 | .cmd_executions = 1, |
| 850 | .cmd_delay_gap = 4, |
| 851 | .post_ssq_wait = 400, |
| 852 | .data_direction = SSQ_NA, |
| 853 | }, |
| 854 | .sp_cmd_addr = { |
| 855 | .address = 1024, |
| 856 | .rowbits = 6, |
| 857 | .bank = 0, |
| 858 | .rank = 0, |
| 859 | }, |
| 860 | .addr_update = { |
| 861 | .inc_rank = 1, |
| 862 | .addr_wrap = 20, |
| 863 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 864 | }, |
| 865 | }; |
| 866 | iosav_write_sequence(BROADCAST_CH, zqcl_sequence, ARRAY_SIZE(zqcl_sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 867 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 868 | /* Execute command queue on all channels. Do it four times. */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 869 | iosav_run_queue(BROADCAST_CH, 4, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 870 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 871 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 872 | /* Wait for ref drained */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 873 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 874 | } |
| 875 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 876 | /* Refresh enable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 877 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 878 | |
| 879 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 880 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 881 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 882 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 883 | |
| 884 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 885 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 886 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 887 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 888 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 889 | iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 890 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 891 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 892 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 893 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 894 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 895 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 896 | } |
| 897 | } |
| 898 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 899 | static const u32 lane_base[] = { |
| 900 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 901 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 902 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 903 | }; |
| 904 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 905 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 906 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 907 | u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 908 | int lane; |
| 909 | int slotrank, slot; |
| 910 | int full_shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 911 | u16 pi_coding_ctrl[NUM_SLOTS]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 912 | |
| 913 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 914 | if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) |
| 915 | full_shift = -ctrl->timings[channel][slotrank].pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 916 | } |
| 917 | |
| 918 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 919 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 920 | case 0: |
| 921 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 922 | pi_coding_ctrl[slot] = 0x7f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 923 | break; |
| 924 | case 1: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 925 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 926 | ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 927 | break; |
| 928 | case 2: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 929 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 930 | ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 931 | break; |
| 932 | case 3: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 933 | pi_coding_ctrl[slot] = |
| 934 | (ctrl->timings[channel][2 * slot].pi_coding + |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 935 | ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 936 | break; |
| 937 | } |
| 938 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 939 | /* Enable CMD XOVER */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 940 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 941 | reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; |
| 942 | reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 943 | reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 944 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 945 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 946 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 947 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 948 | /* Enable CLK XOVER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 949 | reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 950 | reg_logic_delay = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 951 | |
| 952 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 953 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 954 | int offset_pi_code; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 955 | if (shift < 0) |
| 956 | shift = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 957 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 958 | offset_pi_code = ctrl->pi_code_offset + shift; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 959 | |
| 960 | /* Set CLK phase shift */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 961 | reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); |
| 962 | reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 963 | } |
| 964 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 965 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; |
| 966 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 967 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 968 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 969 | reg_io_latency &= ~0xffff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 970 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 971 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 972 | |
| 973 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 974 | int post_timA_min_high = 7, pre_timA_min_high = 7; |
| 975 | int post_timA_max_high = 0, pre_timA_max_high = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 976 | int shift_402x = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 977 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 978 | |
| 979 | if (shift < 0) |
| 980 | shift = 0; |
| 981 | |
| 982 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 983 | post_timA_min_high = MIN(post_timA_min_high, |
| 984 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 985 | timA + shift) >> 6); |
| 986 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 987 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 988 | timA >> 6); |
| 989 | post_timA_max_high = MAX(post_timA_max_high, |
| 990 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 991 | timA + shift) >> 6); |
| 992 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 993 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 994 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 995 | } |
| 996 | |
| 997 | if (pre_timA_max_high - pre_timA_min_high < |
| 998 | post_timA_max_high - post_timA_min_high) |
| 999 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1000 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1001 | else if (pre_timA_max_high - pre_timA_min_high > |
| 1002 | post_timA_max_high - post_timA_min_high) |
| 1003 | shift_402x = -1; |
| 1004 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 1005 | reg_io_latency |= |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1006 | (ctrl->timings[channel][slotrank].io_latency + shift_402x - |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1007 | post_timA_min_high) << (4 * slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1008 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1009 | reg_roundtrip_latency |= |
| 1010 | (ctrl->timings[channel][slotrank].roundtrip_latency + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1011 | shift_402x) << (8 * slotrank); |
| 1012 | |
| 1013 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1014 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1015 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1016 | timA + shift) & 0x3f) |
| 1017 | | |
| 1018 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1019 | rising + shift) << 8) |
| 1020 | | |
| 1021 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1022 | timA + shift - |
| 1023 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 1024 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1025 | falling + shift) << 20)); |
| 1026 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1027 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1028 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1029 | timC + shift) & 0x3f) |
| 1030 | | |
| 1031 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1032 | timB + shift) & 0x3f) << 8) |
| 1033 | | |
| 1034 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1035 | timB + shift) & 0x1c0) << 9) |
| 1036 | | |
| 1037 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1038 | timC + shift) & 0x40) << 13)); |
| 1039 | } |
| 1040 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1041 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1042 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1043 | } |
| 1044 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1045 | static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1046 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1047 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1048 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1049 | iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1050 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1051 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1052 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1053 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1054 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1055 | } |
| 1056 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1057 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1058 | { |
| 1059 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1060 | |
| 1061 | return (MCHBAR32(lane_base[lane] + |
| 1062 | GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1063 | } |
| 1064 | |
| 1065 | struct run { |
| 1066 | int middle; |
| 1067 | int end; |
| 1068 | int start; |
| 1069 | int all; |
| 1070 | int length; |
| 1071 | }; |
| 1072 | |
| 1073 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1074 | { |
| 1075 | int i, ls; |
| 1076 | int bl = 0, bs = 0; |
| 1077 | struct run ret; |
| 1078 | |
| 1079 | ls = 0; |
| 1080 | for (i = 0; i < 2 * sz; i++) |
| 1081 | if (seq[i % sz]) { |
| 1082 | if (i - ls > bl) { |
| 1083 | bl = i - ls; |
| 1084 | bs = ls; |
| 1085 | } |
| 1086 | ls = i + 1; |
| 1087 | } |
| 1088 | if (bl == 0) { |
| 1089 | ret.middle = sz / 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1090 | ret.start = 0; |
| 1091 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1092 | ret.length = sz; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1093 | ret.all = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1094 | return ret; |
| 1095 | } |
| 1096 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1097 | ret.start = bs % sz; |
| 1098 | ret.end = (bs + bl - 1) % sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1099 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1100 | ret.length = bl; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1101 | ret.all = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1102 | |
| 1103 | return ret; |
| 1104 | } |
| 1105 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1106 | static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1107 | { |
| 1108 | int timA; |
| 1109 | int statistics[NUM_LANES][128]; |
| 1110 | int lane; |
| 1111 | |
| 1112 | for (timA = 0; timA < 128; timA++) { |
| 1113 | FOR_ALL_LANES { |
| 1114 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1115 | } |
| 1116 | program_timings(ctrl, channel); |
| 1117 | |
| 1118 | test_timA(ctrl, channel, slotrank); |
| 1119 | |
| 1120 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1121 | statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1122 | } |
| 1123 | } |
| 1124 | FOR_ALL_LANES { |
| 1125 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1126 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1127 | upperA[lane] = rn.end; |
| 1128 | if (upperA[lane] < rn.middle) |
| 1129 | upperA[lane] += 128; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1130 | |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1131 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1132 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1133 | } |
| 1134 | } |
| 1135 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1136 | static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1137 | { |
| 1138 | int timA_delta; |
| 1139 | int statistics[NUM_LANES][51]; |
| 1140 | int lane, i; |
| 1141 | |
| 1142 | memset(statistics, 0, sizeof(statistics)); |
| 1143 | |
| 1144 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1145 | |
| 1146 | FOR_ALL_LANES { |
| 1147 | ctrl->timings[channel][slotrank].lanes[lane].timA |
| 1148 | = upperA[lane] + timA_delta + 0x40; |
| 1149 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1150 | program_timings(ctrl, channel); |
| 1151 | |
| 1152 | for (i = 0; i < 100; i++) { |
| 1153 | test_timA(ctrl, channel, slotrank); |
| 1154 | FOR_ALL_LANES { |
| 1155 | statistics[lane][timA_delta + 25] += |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1156 | does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1157 | } |
| 1158 | } |
| 1159 | } |
| 1160 | FOR_ALL_LANES { |
| 1161 | int last_zero, first_all; |
| 1162 | |
| 1163 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1164 | if (statistics[lane][last_zero + 25]) |
| 1165 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1166 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1167 | last_zero--; |
| 1168 | for (first_all = -25; first_all <= 25; first_all++) |
| 1169 | if (statistics[lane][first_all + 25] == 100) |
| 1170 | break; |
| 1171 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1172 | printram("lane %d: %d, %d\n", lane, last_zero, first_all); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1173 | |
| 1174 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1175 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1176 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1177 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1178 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1179 | } |
| 1180 | } |
| 1181 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1182 | static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1183 | { |
| 1184 | int works[NUM_LANES]; |
| 1185 | int lane; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1186 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1187 | while (1) { |
| 1188 | int all_works = 1, some_works = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1189 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1190 | program_timings(ctrl, channel); |
| 1191 | test_timA(ctrl, channel, slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1192 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1193 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1194 | works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); |
| 1195 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1196 | if (works[lane]) |
| 1197 | some_works = 1; |
| 1198 | else |
| 1199 | all_works = 0; |
| 1200 | } |
| 1201 | if (all_works) |
| 1202 | return 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1203 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1204 | if (!some_works) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1205 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1206 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1207 | channel, slotrank); |
| 1208 | return MAKE_ERR; |
| 1209 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1210 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1211 | printram("4024 -= 2;\n"); |
| 1212 | continue; |
| 1213 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1214 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1215 | printram("4028 += 2;\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1216 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1217 | if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1218 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1219 | channel, slotrank); |
| 1220 | return MAKE_ERR; |
| 1221 | } |
| 1222 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1223 | ctrl->timings[channel][slotrank].lanes[lane].timA += 128; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1224 | upperA[lane] += 128; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1225 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1226 | } |
| 1227 | } |
| 1228 | return 0; |
| 1229 | } |
| 1230 | |
| 1231 | struct timA_minmax { |
| 1232 | int timA_min_high, timA_max_high; |
| 1233 | }; |
| 1234 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1235 | static void pre_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1236 | struct timA_minmax *mnmx) |
| 1237 | { |
| 1238 | int lane; |
| 1239 | mnmx->timA_min_high = 7; |
| 1240 | mnmx->timA_max_high = 0; |
| 1241 | |
| 1242 | FOR_ALL_LANES { |
| 1243 | if (mnmx->timA_min_high > |
| 1244 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1245 | mnmx->timA_min_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1246 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1247 | if (mnmx->timA_max_high < |
| 1248 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1249 | mnmx->timA_max_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1250 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1251 | } |
| 1252 | } |
| 1253 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1254 | static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1255 | struct timA_minmax *mnmx) |
| 1256 | { |
| 1257 | struct timA_minmax post; |
| 1258 | int shift_402x = 0; |
| 1259 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1260 | /* Get changed maxima */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1261 | pre_timA_change(ctrl, channel, slotrank, &post); |
| 1262 | |
| 1263 | if (mnmx->timA_max_high - mnmx->timA_min_high < |
| 1264 | post.timA_max_high - post.timA_min_high) |
| 1265 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1266 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1267 | else if (mnmx->timA_max_high - mnmx->timA_min_high > |
| 1268 | post.timA_max_high - post.timA_min_high) |
| 1269 | shift_402x = -1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1270 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1271 | else |
| 1272 | shift_402x = 0; |
| 1273 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1274 | ctrl->timings[channel][slotrank].io_latency += shift_402x; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1275 | ctrl->timings[channel][slotrank].roundtrip_latency += shift_402x; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1276 | printram("4024 += %d;\n", shift_402x); |
| 1277 | printram("4028 += %d;\n", shift_402x); |
| 1278 | } |
| 1279 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1280 | /* |
| 1281 | * Compensate the skew between DQS and DQs. |
| 1282 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1283 | * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. |
| 1284 | * The controller has to measure and compensate this skew for every byte-lane. By delaying |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1285 | * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1286 | * that one byte-lane's DQs signals have the same routing delay. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1287 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1288 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling |
| 1289 | * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates |
| 1290 | * over all possible values to do a full phase shift and issues read commands. With DQS and |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1291 | * DQ in phase the data being read is expected to alternate on every byte: |
| 1292 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1293 | * 0xFF 0x00 0xFF ... |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1294 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1295 | * Once the controller has detected this pattern a bit in the result register is set for the |
| 1296 | * current phase shift. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1297 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1298 | int read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1299 | { |
| 1300 | int channel, slotrank, lane; |
| 1301 | int err; |
| 1302 | |
| 1303 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1304 | int all_high, some_high; |
| 1305 | int upperA[NUM_LANES]; |
| 1306 | struct timA_minmax mnmx; |
| 1307 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1308 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1309 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1310 | iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1311 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1312 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1313 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1314 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1315 | MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1316 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1317 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1318 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1319 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1320 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1321 | discover_timA_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1322 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1323 | all_high = 1; |
| 1324 | some_high = 0; |
| 1325 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1326 | if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1327 | some_high = 1; |
| 1328 | else |
| 1329 | all_high = 0; |
| 1330 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1331 | |
| 1332 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1333 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1334 | printram("4028--;\n"); |
| 1335 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1336 | ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1337 | upperA[lane] -= 0x40; |
| 1338 | |
| 1339 | } |
| 1340 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1341 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1342 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1343 | printram("4024++;\n"); |
| 1344 | printram("4028++;\n"); |
| 1345 | } |
| 1346 | |
| 1347 | program_timings(ctrl, channel); |
| 1348 | |
| 1349 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1350 | |
| 1351 | err = discover_402x(ctrl, channel, slotrank, upperA); |
| 1352 | if (err) |
| 1353 | return err; |
| 1354 | |
| 1355 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1356 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1357 | |
| 1358 | discover_timA_fine(ctrl, channel, slotrank, upperA); |
| 1359 | |
| 1360 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1361 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1362 | |
| 1363 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1364 | ctrl->timings[channel][slotrank].lanes[lane].timA -= |
| 1365 | mnmx.timA_min_high * 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1366 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1367 | ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1368 | printram("4028 -= %d;\n", mnmx.timA_min_high); |
| 1369 | |
| 1370 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1371 | |
| 1372 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1373 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1374 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1375 | |
| 1376 | printram("final results:\n"); |
| 1377 | FOR_ALL_LANES |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1378 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1379 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1380 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1381 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1382 | |
| 1383 | toggle_io_reset(); |
| 1384 | } |
| 1385 | |
| 1386 | FOR_ALL_POPULATED_CHANNELS { |
| 1387 | program_timings(ctrl, channel); |
| 1388 | } |
| 1389 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1390 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1391 | } |
| 1392 | return 0; |
| 1393 | } |
| 1394 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1395 | static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1396 | { |
| 1397 | int lane; |
| 1398 | |
| 1399 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1400 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1401 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1402 | } |
| 1403 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1404 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1405 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1406 | iosav_write_misc_write_sequence(ctrl, channel, slotrank, |
| 1407 | MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1408 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1409 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1410 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1411 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1412 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1413 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1414 | const struct iosav_ssq rd_sequence[] = { |
| 1415 | /* DRAM command PREA */ |
| 1416 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1417 | .sp_cmd_ctrl = { |
| 1418 | .command = IOSAV_PRE, |
| 1419 | .ranksel_ap = 1, |
| 1420 | }, |
| 1421 | .subseq_ctrl = { |
| 1422 | .cmd_executions = 1, |
| 1423 | .cmd_delay_gap = 3, |
| 1424 | .post_ssq_wait = ctrl->tRP, |
| 1425 | .data_direction = SSQ_NA, |
| 1426 | }, |
| 1427 | .sp_cmd_addr = { |
| 1428 | .address = 1024, |
| 1429 | .rowbits = 6, |
| 1430 | .bank = 0, |
| 1431 | .rank = slotrank, |
| 1432 | }, |
| 1433 | .addr_update = { |
| 1434 | .addr_wrap = 18, |
| 1435 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1436 | }, |
| 1437 | /* DRAM command ACT */ |
| 1438 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1439 | .sp_cmd_ctrl = { |
| 1440 | .command = IOSAV_ACT, |
| 1441 | .ranksel_ap = 1, |
| 1442 | }, |
| 1443 | .subseq_ctrl = { |
| 1444 | .cmd_executions = 8, |
| 1445 | .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), |
| 1446 | .post_ssq_wait = ctrl->CAS, |
| 1447 | .data_direction = SSQ_NA, |
| 1448 | }, |
| 1449 | .sp_cmd_addr = { |
| 1450 | .address = 0, |
| 1451 | .rowbits = 6, |
| 1452 | .bank = 0, |
| 1453 | .rank = slotrank, |
| 1454 | }, |
| 1455 | .addr_update = { |
| 1456 | .inc_bank = 1, |
| 1457 | .addr_wrap = 18, |
| 1458 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1459 | }, |
| 1460 | /* DRAM command RD */ |
| 1461 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1462 | .sp_cmd_ctrl = { |
| 1463 | .command = IOSAV_RD, |
| 1464 | .ranksel_ap = 1, |
| 1465 | }, |
| 1466 | .subseq_ctrl = { |
| 1467 | .cmd_executions = 500, |
| 1468 | .cmd_delay_gap = 4, |
| 1469 | .post_ssq_wait = MAX(ctrl->tRTP, 8), |
| 1470 | .data_direction = SSQ_RD, |
| 1471 | }, |
| 1472 | .sp_cmd_addr = { |
| 1473 | .address = 0, |
| 1474 | .rowbits = 0, |
| 1475 | .bank = 0, |
| 1476 | .rank = slotrank, |
| 1477 | }, |
| 1478 | .addr_update = { |
| 1479 | .inc_addr_8 = 1, |
| 1480 | .addr_wrap = 18, |
| 1481 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1482 | }, |
| 1483 | /* DRAM command PREA */ |
| 1484 | [3] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1485 | .sp_cmd_ctrl = { |
| 1486 | .command = IOSAV_PRE, |
| 1487 | .ranksel_ap = 1, |
| 1488 | }, |
| 1489 | .subseq_ctrl = { |
| 1490 | .cmd_executions = 1, |
| 1491 | .cmd_delay_gap = 3, |
| 1492 | .post_ssq_wait = ctrl->tRP, |
| 1493 | .data_direction = SSQ_NA, |
| 1494 | }, |
| 1495 | .sp_cmd_addr = { |
| 1496 | .address = 1024, |
| 1497 | .rowbits = 6, |
| 1498 | .bank = 0, |
| 1499 | .rank = slotrank, |
| 1500 | }, |
| 1501 | .addr_update = { |
| 1502 | .addr_wrap = 18, |
| 1503 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1504 | }, |
| 1505 | }; |
| 1506 | iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1507 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1508 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1509 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1510 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1511 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1512 | } |
| 1513 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1514 | static void timC_threshold_process(int *data, const int count) |
| 1515 | { |
| 1516 | int min = data[0]; |
| 1517 | int max = min; |
| 1518 | int i; |
| 1519 | for (i = 1; i < count; i++) { |
| 1520 | if (min > data[i]) |
| 1521 | min = data[i]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1522 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1523 | if (max < data[i]) |
| 1524 | max = data[i]; |
| 1525 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1526 | int threshold = min / 2 + max / 2; |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1527 | for (i = 0; i < count; i++) |
| 1528 | data[i] = data[i] > threshold; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1529 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1530 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1531 | } |
| 1532 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1533 | static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) |
| 1534 | { |
| 1535 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1536 | int stats[NUM_LANES][MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1537 | int lane; |
| 1538 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1539 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1540 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1541 | iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1542 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1543 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1544 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1545 | |
| 1546 | for (timC = 0; timC <= MAX_TIMC; timC++) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1547 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1548 | program_timings(ctrl, channel); |
| 1549 | |
| 1550 | test_timC(ctrl, channel, slotrank); |
| 1551 | |
| 1552 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1553 | stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1554 | } |
| 1555 | } |
| 1556 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1557 | struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1558 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1559 | if (rn.all || rn.length < 8) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1560 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1561 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1562 | /* |
| 1563 | * With command training not being done yet, the lane can be erroneous. |
| 1564 | * Take the average as reference and try again to find a run. |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1565 | */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1566 | timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1567 | rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1568 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1569 | if (rn.all || rn.length < 8) { |
| 1570 | printk(BIOS_EMERG, "timC recovery failed\n"); |
| 1571 | return MAKE_ERR; |
| 1572 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1573 | } |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1574 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1575 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1576 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1577 | } |
| 1578 | return 0; |
| 1579 | } |
| 1580 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1581 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1582 | { |
| 1583 | int channel, ret = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1584 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1585 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1586 | ret++; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1587 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1588 | return ret; |
| 1589 | } |
| 1590 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1591 | /* Each cacheline is 64 bits long */ |
| 1592 | static void program_wdb_pattern_length(int channel, const unsigned int num_cachelines) |
| 1593 | { |
| 1594 | MCHBAR8(IOSAV_DATA_CTL_ch(channel)) = num_cachelines / 8 - 1; |
| 1595 | } |
| 1596 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1597 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1598 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1599 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1600 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1601 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1602 | for (j = 0; j < 16; j++) |
| 1603 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1604 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1605 | sfence(); |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1606 | |
| 1607 | program_wdb_pattern_length(channel, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1608 | } |
| 1609 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1610 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1611 | { |
| 1612 | int ret = 0; |
| 1613 | int channel; |
| 1614 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1615 | return ret; |
| 1616 | } |
| 1617 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1618 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1619 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1620 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1621 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1622 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1623 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1624 | for (j = 0; j < 16; j++) |
| 1625 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1626 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1627 | for (j = 0; j < 16; j++) |
| 1628 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1629 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1630 | sfence(); |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1631 | |
| 1632 | program_wdb_pattern_length(channel, 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1633 | } |
| 1634 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1635 | static void precharge(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1636 | { |
| 1637 | int channel, slotrank, lane; |
| 1638 | |
| 1639 | FOR_ALL_POPULATED_CHANNELS { |
| 1640 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1641 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 1642 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1643 | } |
| 1644 | |
| 1645 | program_timings(ctrl, channel); |
| 1646 | |
| 1647 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1648 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1649 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1650 | iosav_write_read_mpr_sequence( |
| 1651 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1652 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1653 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1654 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1655 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1656 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1657 | } |
| 1658 | |
| 1659 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1660 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 1661 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1662 | } |
| 1663 | |
| 1664 | program_timings(ctrl, channel); |
| 1665 | |
| 1666 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1667 | wait_for_iosav(channel); |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1668 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1669 | iosav_write_read_mpr_sequence( |
| 1670 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1671 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1672 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1673 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1674 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1675 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1676 | } |
| 1677 | } |
| 1678 | } |
| 1679 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1680 | static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1681 | { |
| 1682 | /* enable DQs on this slotrank */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1683 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 7); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1684 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1685 | wait_for_iosav(channel); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1686 | |
| 1687 | const struct iosav_ssq sequence[] = { |
| 1688 | /* DRAM command NOP */ |
| 1689 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1690 | .sp_cmd_ctrl = { |
| 1691 | .command = IOSAV_NOP, |
| 1692 | .ranksel_ap = 1, |
| 1693 | }, |
| 1694 | .subseq_ctrl = { |
| 1695 | .cmd_executions = 1, |
| 1696 | .cmd_delay_gap = 3, |
| 1697 | .post_ssq_wait = ctrl->CWL + ctrl->tWLO, |
| 1698 | .data_direction = SSQ_WR, |
| 1699 | }, |
| 1700 | .sp_cmd_addr = { |
| 1701 | .address = 8, |
| 1702 | .rowbits = 0, |
| 1703 | .bank = 0, |
| 1704 | .rank = slotrank, |
| 1705 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1706 | }, |
| 1707 | /* DRAM command NOP */ |
| 1708 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1709 | .sp_cmd_ctrl = { |
| 1710 | .command = IOSAV_NOP_ALT, |
| 1711 | .ranksel_ap = 1, |
| 1712 | }, |
| 1713 | .subseq_ctrl = { |
| 1714 | .cmd_executions = 1, |
| 1715 | .cmd_delay_gap = 3, |
| 1716 | .post_ssq_wait = ctrl->CAS + 38, |
| 1717 | .data_direction = SSQ_RD, |
| 1718 | }, |
| 1719 | .sp_cmd_addr = { |
| 1720 | .address = 4, |
| 1721 | .rowbits = 0, |
| 1722 | .bank = 0, |
| 1723 | .rank = slotrank, |
| 1724 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1725 | }, |
| 1726 | }; |
| 1727 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1728 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1729 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1730 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1731 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1732 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1733 | |
| 1734 | /* disable DQs on this slotrank */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1735 | write_mrreg(ctrl, channel, slotrank, 1, |
| 1736 | make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1737 | } |
| 1738 | |
| 1739 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 1740 | { |
| 1741 | int timB; |
| 1742 | int statistics[NUM_LANES][128]; |
| 1743 | int lane; |
| 1744 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1745 | MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1746 | |
| 1747 | for (timB = 0; timB < 128; timB++) { |
| 1748 | FOR_ALL_LANES { |
| 1749 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 1750 | } |
| 1751 | program_timings(ctrl, channel); |
| 1752 | |
| 1753 | test_timB(ctrl, channel, slotrank); |
| 1754 | |
| 1755 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1756 | statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + |
| 1757 | GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> |
| 1758 | (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1759 | } |
| 1760 | } |
| 1761 | FOR_ALL_LANES { |
| 1762 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1763 | /* |
| 1764 | * timC is a direct function of timB's 6 LSBs. Some tests increments the value |
| 1765 | * of timB by a small value, which might cause the 6-bit value to overflow if |
| 1766 | * it's close to 0x3f. Increment the value by a small offset if it's likely |
| 1767 | * to overflow, to make sure it won't overflow while running tests and bricks |
| 1768 | * the system due to a non matching timC. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1769 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1770 | * TODO: find out why some tests (edge write discovery) increment timB. |
| 1771 | */ |
| 1772 | if ((rn.start & 0x3f) == 0x3e) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1773 | rn.start += 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1774 | else if ((rn.start & 0x3f) == 0x3f) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1775 | rn.start += 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1776 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1777 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 1778 | if (rn.all) { |
| 1779 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 1780 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1781 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1782 | return MAKE_ERR; |
| 1783 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1784 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1785 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1786 | } |
| 1787 | return 0; |
| 1788 | } |
| 1789 | |
| 1790 | static int get_timB_high_adjust(u64 val) |
| 1791 | { |
| 1792 | int i; |
| 1793 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1794 | /* DQS is good enough */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1795 | if (val == 0xffffffffffffffffLL) |
| 1796 | return 0; |
| 1797 | |
| 1798 | if (val >= 0xf000000000000000LL) { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1799 | /* DQS is late, needs negative adjustment */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1800 | for (i = 0; i < 8; i++) |
| 1801 | if (val << (8 * (7 - i) + 4)) |
| 1802 | return -i; |
| 1803 | } else { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1804 | /* DQS is early, needs positive adjustment */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1805 | for (i = 0; i < 8; i++) |
| 1806 | if (val >> (8 * (7 - i) + 4)) |
| 1807 | return i; |
| 1808 | } |
| 1809 | return 8; |
| 1810 | } |
| 1811 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1812 | static void train_write_flyby(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1813 | { |
| 1814 | int channel, slotrank, lane, old; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1815 | MCHBAR32(GDCRTRAININGMOD) = 0x200; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1816 | FOR_ALL_POPULATED_CHANNELS { |
| 1817 | fill_pattern1(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1818 | } |
| 1819 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1820 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1821 | /* Reset read and write WDB pointers */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1822 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1823 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1824 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1825 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1826 | iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1827 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1828 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1829 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1830 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1831 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1832 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1833 | const struct iosav_ssq rd_sequence[] = { |
| 1834 | /* DRAM command PREA */ |
| 1835 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1836 | .sp_cmd_ctrl = { |
| 1837 | .command = IOSAV_PRE, |
| 1838 | .ranksel_ap = 1, |
| 1839 | }, |
| 1840 | .subseq_ctrl = { |
| 1841 | .cmd_executions = 1, |
| 1842 | .cmd_delay_gap = 3, |
| 1843 | .post_ssq_wait = ctrl->tRP, |
| 1844 | .data_direction = SSQ_NA, |
| 1845 | }, |
| 1846 | .sp_cmd_addr = { |
| 1847 | .address = 1024, |
| 1848 | .rowbits = 6, |
| 1849 | .bank = 0, |
| 1850 | .rank = slotrank, |
| 1851 | }, |
| 1852 | .addr_update = { |
| 1853 | .addr_wrap = 18, |
| 1854 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1855 | }, |
| 1856 | /* DRAM command ACT */ |
| 1857 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1858 | .sp_cmd_ctrl = { |
| 1859 | .command = IOSAV_ACT, |
| 1860 | .ranksel_ap = 1, |
| 1861 | }, |
| 1862 | .subseq_ctrl = { |
| 1863 | .cmd_executions = 1, |
| 1864 | .cmd_delay_gap = 3, |
| 1865 | .post_ssq_wait = ctrl->tRCD, |
| 1866 | .data_direction = SSQ_NA, |
| 1867 | }, |
| 1868 | .sp_cmd_addr = { |
| 1869 | .address = 0, |
| 1870 | .rowbits = 6, |
| 1871 | .bank = 0, |
| 1872 | .rank = slotrank, |
| 1873 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1874 | }, |
| 1875 | /* DRAM command RD */ |
| 1876 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1877 | .sp_cmd_ctrl = { |
| 1878 | .command = IOSAV_RD, |
| 1879 | .ranksel_ap = 3, |
| 1880 | }, |
| 1881 | .subseq_ctrl = { |
| 1882 | .cmd_executions = 1, |
| 1883 | .cmd_delay_gap = 3, |
| 1884 | .post_ssq_wait = ctrl->tRP + |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1885 | ctrl->timings[channel][slotrank].roundtrip_latency + |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1886 | ctrl->timings[channel][slotrank].io_latency, |
| 1887 | .data_direction = SSQ_RD, |
| 1888 | }, |
| 1889 | .sp_cmd_addr = { |
| 1890 | .address = 8, |
| 1891 | .rowbits = 6, |
| 1892 | .bank = 0, |
| 1893 | .rank = slotrank, |
| 1894 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1895 | }, |
| 1896 | }; |
| 1897 | iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1898 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1899 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1900 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1901 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1902 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1903 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1904 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 1905 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1906 | GDCRTRAININGRESULT2(channel))) << 32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1907 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 1908 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 1909 | get_timB_high_adjust(res) * 64; |
| 1910 | |
| 1911 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1912 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, |
| 1913 | old, ctrl->timings[channel][slotrank].lanes[lane].timB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1914 | } |
| 1915 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1916 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1917 | } |
| 1918 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1919 | static void write_op(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1920 | { |
| 1921 | int slotrank; |
| 1922 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1923 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1924 | |
| 1925 | /* choose an existing rank. */ |
| 1926 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 1927 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1928 | iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1929 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1930 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1931 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1932 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1933 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1934 | } |
| 1935 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1936 | /* |
| 1937 | * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1938 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1939 | * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different |
| 1940 | * times with respect to command, address and clock signals. By delaying either all DQ/DQS or |
| 1941 | * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the |
| 1942 | * CLK/ADDR/CMD signals have the same routing delay. |
| 1943 | * |
| 1944 | * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, |
| 1945 | * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data |
| 1946 | * lanes (DQ). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1947 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1948 | int write_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1949 | { |
| 1950 | int channel, slotrank, lane; |
| 1951 | int err; |
| 1952 | |
| 1953 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1954 | MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1955 | |
| 1956 | FOR_ALL_POPULATED_CHANNELS { |
| 1957 | write_op(ctrl, channel); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1958 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1959 | } |
| 1960 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1961 | /* Refresh disable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1962 | MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1963 | FOR_ALL_POPULATED_CHANNELS { |
| 1964 | write_op(ctrl, channel); |
| 1965 | } |
| 1966 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1967 | /* Enable write leveling on all ranks |
| 1968 | Disable all DQ outputs |
| 1969 | Only NOP is allowed in this mode */ |
| 1970 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 1971 | write_mrreg(ctrl, channel, slotrank, 1, |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1972 | make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1973 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1974 | MCHBAR32(GDCRTRAININGMOD) = 0x108052; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1975 | |
| 1976 | toggle_io_reset(); |
| 1977 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1978 | /* Set any valid value for timB, it gets corrected later */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1979 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1980 | err = discover_timB(ctrl, channel, slotrank); |
| 1981 | if (err) |
| 1982 | return err; |
| 1983 | } |
| 1984 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1985 | /* Disable write leveling on all ranks */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1986 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1987 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1988 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1989 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1990 | |
| 1991 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1992 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1993 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1994 | /* Refresh enable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1995 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1996 | |
| 1997 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1998 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1999 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 2000 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2001 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2002 | iosav_write_zqcs_sequence(channel, 0, 4, 101, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2003 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2004 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2005 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2006 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2007 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2008 | } |
| 2009 | |
| 2010 | toggle_io_reset(); |
| 2011 | |
| 2012 | printram("CPE\n"); |
| 2013 | precharge(ctrl); |
| 2014 | printram("CPF\n"); |
| 2015 | |
| 2016 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2017 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2018 | } |
| 2019 | |
| 2020 | FOR_ALL_POPULATED_CHANNELS { |
| 2021 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2022 | } |
| 2023 | |
| 2024 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2025 | err = discover_timC(ctrl, channel, slotrank); |
| 2026 | if (err) |
| 2027 | return err; |
| 2028 | } |
| 2029 | |
| 2030 | FOR_ALL_POPULATED_CHANNELS |
| 2031 | program_timings(ctrl, channel); |
| 2032 | |
| 2033 | /* measure and adjust timB timings */ |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2034 | train_write_flyby(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2035 | |
| 2036 | FOR_ALL_POPULATED_CHANNELS |
| 2037 | program_timings(ctrl, channel); |
| 2038 | |
| 2039 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2040 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2041 | } |
| 2042 | return 0; |
| 2043 | } |
| 2044 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2045 | static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2046 | { |
| 2047 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2048 | int timC_delta; |
| 2049 | int lanes_ok = 0; |
| 2050 | int ctr = 0; |
| 2051 | int lane; |
| 2052 | |
| 2053 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2054 | FOR_ALL_LANES { |
| 2055 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2056 | saved_rt.lanes[lane].timC + timC_delta; |
| 2057 | } |
| 2058 | program_timings(ctrl, channel); |
| 2059 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2060 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2061 | } |
| 2062 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 2063 | /* Reset read WDB pointer */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2064 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2065 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2066 | wait_for_iosav(channel); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2067 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2068 | iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2069 | |
| 2070 | /* Program LFSR for the RD/WR subsequences */ |
| 2071 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
| 2072 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2073 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2074 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2075 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2076 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2077 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2078 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2079 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2080 | |
| 2081 | if (r32 == 0) |
| 2082 | lanes_ok |= 1 << lane; |
| 2083 | } |
| 2084 | ctr++; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2085 | if (lanes_ok == ((1 << ctrl->lanes) - 1)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2086 | break; |
| 2087 | } |
| 2088 | |
| 2089 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2090 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2091 | return lanes_ok != ((1 << ctrl->lanes) - 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2092 | } |
| 2093 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2094 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2095 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2096 | unsigned int i, j; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2097 | unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; |
| 2098 | unsigned int step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2099 | |
| 2100 | if (patno) { |
| 2101 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2102 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2103 | for (i = 0; i < 32; i++) { |
| 2104 | for (j = 0; j < 16; j++) { |
| 2105 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2106 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2107 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2108 | val = ~val; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2109 | |
| 2110 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2111 | } |
| 2112 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2113 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2114 | for (i = 0; i < ARRAY_SIZE(pattern); i++) { |
| 2115 | for (j = 0; j < 16; j++) { |
| 2116 | const u32 val = pattern[i][j]; |
| 2117 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
| 2118 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2119 | } |
| 2120 | sfence(); |
| 2121 | } |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 2122 | |
| 2123 | program_wdb_pattern_length(channel, 256); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2124 | } |
| 2125 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2126 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2127 | { |
| 2128 | int channel, slotrank; |
| 2129 | |
| 2130 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2131 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2132 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2133 | /* Choose an existing rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2134 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2135 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2136 | iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2137 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2138 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2139 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2140 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2141 | wait_for_iosav(channel); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2142 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2143 | } |
| 2144 | |
| 2145 | /* refresh disable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2146 | MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2147 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2148 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2149 | |
| 2150 | /* choose an existing rank. */ |
| 2151 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2152 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2153 | iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2154 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2155 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2156 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2157 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2158 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2159 | } |
| 2160 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2161 | /* JEDEC reset */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2162 | dram_jedecreset(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2163 | |
| 2164 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2165 | dram_mrscommands(ctrl); |
| 2166 | |
| 2167 | toggle_io_reset(); |
| 2168 | } |
| 2169 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2170 | #define CT_MIN_PI -127 |
| 2171 | #define CT_MAX_PI 128 |
| 2172 | #define CT_PI_LENGTH (CT_MAX_PI - CT_MIN_PI + 1) |
| 2173 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2174 | #define MIN_C320C_LEN 13 |
| 2175 | |
| 2176 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 2177 | { |
| 2178 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 2179 | int slotrank; |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2180 | int command_pi; |
| 2181 | int stat[NUM_SLOTRANKS][CT_PI_LENGTH]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2182 | int delta = 0; |
| 2183 | |
| 2184 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2185 | |
| 2186 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2187 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2188 | } |
| 2189 | |
| 2190 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2191 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2192 | MCHBAR32(TC_RAP_ch(channel)) = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2193 | (ctrl->tRRD << 0) |
| 2194 | | (ctrl->tRTP << 4) |
| 2195 | | (ctrl->tCKE << 8) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2196 | | (ctrl->tWTR << 12) |
| 2197 | | (ctrl->tFAW << 16) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2198 | | (ctrl->tWR << 24) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2199 | | (ctrl->cmd_stretch[channel] << 30); |
| 2200 | |
| 2201 | if (ctrl->cmd_stretch[channel] == 2) |
| 2202 | delta = 2; |
| 2203 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2204 | delta = 4; |
| 2205 | |
| 2206 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2207 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2208 | } |
| 2209 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2210 | for (command_pi = CT_MIN_PI; command_pi < CT_MAX_PI; command_pi++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2211 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2212 | ctrl->timings[channel][slotrank].pi_coding = command_pi; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2213 | } |
| 2214 | program_timings(ctrl, channel); |
| 2215 | reprogram_320c(ctrl); |
| 2216 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2217 | stat[slotrank][command_pi - CT_MIN_PI] = |
| 2218 | test_command_training(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2219 | } |
| 2220 | } |
| 2221 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2222 | struct run rn = get_longest_zero_run(stat[slotrank], CT_PI_LENGTH - 1); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2223 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2224 | ctrl->timings[channel][slotrank].pi_coding = rn.middle + CT_MIN_PI; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2225 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2226 | channel, slotrank, rn.start, rn.middle, rn.end); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2227 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2228 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2229 | FOR_ALL_POPULATED_RANKS { |
| 2230 | ctrl->timings[channel][slotrank] = |
| 2231 | saved_timings[channel][slotrank]; |
| 2232 | } |
| 2233 | return MAKE_ERR; |
| 2234 | } |
| 2235 | } |
| 2236 | |
| 2237 | return 0; |
| 2238 | } |
| 2239 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2240 | /* |
| 2241 | * Adjust CMD phase shift and try multiple command rates. |
| 2242 | * A command rate of 2T doubles the time needed for address and command decode. |
| 2243 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2244 | int command_training(ramctr_timing *ctrl) |
| 2245 | { |
| 2246 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2247 | |
| 2248 | FOR_ALL_POPULATED_CHANNELS { |
| 2249 | fill_pattern5(ctrl, channel, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2250 | } |
| 2251 | |
| 2252 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2253 | int cmdrate, err; |
| 2254 | |
| 2255 | /* |
| 2256 | * Dual DIMM per channel: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2257 | * Issue: |
| 2258 | * While c320c discovery seems to succeed raminit will fail in write training. |
| 2259 | * |
| 2260 | * Workaround: |
| 2261 | * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. |
| 2262 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2263 | * |
| 2264 | * Single DIMM per channel: |
| 2265 | * Try command rate 1T and 2T |
| 2266 | */ |
| 2267 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2268 | if (ctrl->tCMD) |
| 2269 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 2270 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2271 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 2272 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2273 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2274 | |
| 2275 | if (!err) |
| 2276 | break; |
| 2277 | } |
| 2278 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2279 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2280 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 2281 | return err; |
| 2282 | } |
| 2283 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2284 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2285 | } |
| 2286 | |
| 2287 | FOR_ALL_POPULATED_CHANNELS |
| 2288 | program_timings(ctrl, channel); |
| 2289 | |
| 2290 | reprogram_320c(ctrl); |
| 2291 | return 0; |
| 2292 | } |
| 2293 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2294 | static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2295 | { |
| 2296 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2297 | int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2298 | int lane; |
| 2299 | |
| 2300 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2301 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2302 | ctrl->timings[channel][slotrank].lanes[lane].rising = edge; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2303 | ctrl->timings[channel][slotrank].lanes[lane].falling = edge; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2304 | } |
| 2305 | program_timings(ctrl, channel); |
| 2306 | |
| 2307 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2308 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2309 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2310 | } |
| 2311 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2312 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2313 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2314 | iosav_write_read_mpr_sequence( |
| 2315 | channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2316 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2317 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2318 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2319 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2320 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2321 | |
| 2322 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2323 | stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2324 | } |
| 2325 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2326 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2327 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2328 | struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2329 | edges[lane] = rn.middle; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2330 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2331 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2332 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, |
| 2333 | slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2334 | return MAKE_ERR; |
| 2335 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2336 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2337 | } |
| 2338 | return 0; |
| 2339 | } |
| 2340 | |
| 2341 | int discover_edges(ramctr_timing *ctrl) |
| 2342 | { |
| 2343 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2344 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2345 | int channel, slotrank, lane; |
| 2346 | int err; |
| 2347 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2348 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2349 | |
| 2350 | toggle_io_reset(); |
| 2351 | |
| 2352 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2353 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2354 | } |
| 2355 | |
| 2356 | FOR_ALL_POPULATED_CHANNELS { |
| 2357 | fill_pattern0(ctrl, channel, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2358 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2359 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2360 | } |
| 2361 | |
| 2362 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2363 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 2364 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2365 | } |
| 2366 | |
| 2367 | program_timings(ctrl, channel); |
| 2368 | |
| 2369 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2370 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2371 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2372 | iosav_write_read_mpr_sequence( |
| 2373 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2374 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2375 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2376 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2377 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2378 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2379 | } |
| 2380 | |
| 2381 | /* XXX: check any measured value ? */ |
| 2382 | |
| 2383 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2384 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2385 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2386 | } |
| 2387 | |
| 2388 | program_timings(ctrl, channel); |
| 2389 | |
| 2390 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2391 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2392 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2393 | iosav_write_read_mpr_sequence( |
| 2394 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2395 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2396 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2397 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2398 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2399 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2400 | } |
| 2401 | |
| 2402 | /* XXX: check any measured value ? */ |
| 2403 | |
| 2404 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2405 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2406 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2407 | } |
| 2408 | |
| 2409 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2410 | } |
| 2411 | |
Angel Pons | 0c3936e | 2020-03-22 12:49:27 +0100 | [diff] [blame] | 2412 | /* |
| 2413 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2414 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2415 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2416 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2417 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2418 | |
| 2419 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2420 | err = discover_edges_real(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2421 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2422 | if (err) |
| 2423 | return err; |
| 2424 | } |
| 2425 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2426 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2427 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2428 | |
| 2429 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2430 | err = discover_edges_real(ctrl, channel, slotrank, |
| 2431 | rising_edges[channel][slotrank]); |
| 2432 | if (err) |
| 2433 | return err; |
| 2434 | } |
| 2435 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2436 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2437 | |
| 2438 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2439 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2440 | falling_edges[channel][slotrank][lane]; |
| 2441 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2442 | rising_edges[channel][slotrank][lane]; |
| 2443 | } |
| 2444 | |
| 2445 | FOR_ALL_POPULATED_CHANNELS { |
| 2446 | program_timings(ctrl, channel); |
| 2447 | } |
| 2448 | |
| 2449 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2450 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2451 | } |
| 2452 | return 0; |
| 2453 | } |
| 2454 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2455 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2456 | { |
| 2457 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2458 | u32 raw_stats[MAX_EDGE_TIMING + 1]; |
| 2459 | int stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2460 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 2461 | int lane, i; |
| 2462 | int lower[NUM_LANES]; |
| 2463 | int upper[NUM_LANES]; |
| 2464 | int pat; |
| 2465 | |
| 2466 | FOR_ALL_LANES { |
| 2467 | lower[lane] = 0; |
| 2468 | upper[lane] = MAX_EDGE_TIMING; |
| 2469 | } |
| 2470 | |
| 2471 | for (i = 0; i < 3; i++) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2472 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2473 | printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); |
| 2474 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2475 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2476 | fill_pattern5(ctrl, channel, pat); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2477 | printram("using pattern %d\n", pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2478 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2479 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2480 | FOR_ALL_LANES { |
| 2481 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2482 | rising = edge; |
| 2483 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2484 | falling = edge; |
| 2485 | } |
| 2486 | program_timings(ctrl, channel); |
| 2487 | |
| 2488 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2489 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2490 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2491 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2492 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2493 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2494 | iosav_write_data_write_sequence(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2495 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2496 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2497 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2498 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2499 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2500 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2501 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2502 | } |
| 2503 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2504 | /* FIXME: This register only exists on Ivy Bridge */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2505 | raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2506 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2507 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2508 | FOR_ALL_LANES { |
| 2509 | struct run rn; |
| 2510 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2511 | stats[edge] = !!(raw_stats[edge] & (1 << lane)); |
| 2512 | |
| 2513 | rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); |
| 2514 | |
| 2515 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " |
| 2516 | "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, |
| 2517 | rn.middle, rn.end, rn.start + ctrl->edge_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2518 | rn.end - ctrl->edge_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2519 | |
| 2520 | lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 2521 | upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 2522 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2523 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2524 | if (rn.all || (lower[lane] > upper[lane])) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2525 | printk(BIOS_EMERG, "edge write discovery failed: " |
| 2526 | "%d, %d, %d\n", channel, slotrank, lane); |
| 2527 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2528 | return MAKE_ERR; |
| 2529 | } |
| 2530 | } |
| 2531 | } |
| 2532 | } |
| 2533 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2534 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2535 | printram("CPA\n"); |
| 2536 | return 0; |
| 2537 | } |
| 2538 | |
| 2539 | int discover_edges_write(ramctr_timing *ctrl) |
| 2540 | { |
| 2541 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2542 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2543 | int channel, slotrank, lane, err; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2544 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2545 | /* |
| 2546 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2547 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2548 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2549 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2550 | printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2551 | |
| 2552 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2553 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2554 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2555 | if (err) |
| 2556 | return err; |
| 2557 | } |
| 2558 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2559 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2560 | printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2561 | |
| 2562 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2563 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2564 | rising_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2565 | if (err) |
| 2566 | return err; |
| 2567 | } |
| 2568 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2569 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2570 | |
| 2571 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2572 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2573 | falling_edges[channel][slotrank][lane]; |
| 2574 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2575 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2576 | rising_edges[channel][slotrank][lane]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2577 | } |
| 2578 | |
| 2579 | FOR_ALL_POPULATED_CHANNELS |
| 2580 | program_timings(ctrl, channel); |
| 2581 | |
| 2582 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2583 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2584 | } |
| 2585 | return 0; |
| 2586 | } |
| 2587 | |
| 2588 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 2589 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2590 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2591 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2592 | iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2593 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2594 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2595 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2596 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2597 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2598 | } |
| 2599 | |
| 2600 | int discover_timC_write(ramctr_timing *ctrl) |
| 2601 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2602 | const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2603 | int i, pat; |
| 2604 | |
| 2605 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2606 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2607 | int channel, slotrank, lane; |
| 2608 | |
| 2609 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2610 | lower[channel][slotrank][lane] = 0; |
| 2611 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 2612 | } |
| 2613 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2614 | /* |
| 2615 | * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2616 | * FIXME: This must only be done on Ivy Bridge. |
| 2617 | */ |
| 2618 | MCHBAR32(MCMNTS_SPARE) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2619 | printram("discover timC write:\n"); |
| 2620 | |
| 2621 | for (i = 0; i < 3; i++) |
| 2622 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2623 | |
| 2624 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
| 2625 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), |
| 2626 | ~0x3f000000, rege3c_b24[i] << 24); |
| 2627 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2628 | udelay(2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2629 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2630 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2631 | FOR_ALL_POPULATED_RANKS { |
| 2632 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2633 | u32 raw_stats[MAX_TIMC + 1]; |
| 2634 | int stats[MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2635 | |
| 2636 | /* Make sure rn.start < rn.end */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2637 | stats[MAX_TIMC] = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2638 | |
| 2639 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2640 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2641 | for (timC = 0; timC < MAX_TIMC; timC++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2642 | FOR_ALL_LANES { |
| 2643 | ctrl->timings[channel][slotrank] |
| 2644 | .lanes[lane].timC = timC; |
| 2645 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2646 | program_timings(ctrl, channel); |
| 2647 | |
| 2648 | test_timC_write (ctrl, channel, slotrank); |
| 2649 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2650 | /* FIXME: Another IVB-only register! */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2651 | raw_stats[timC] = MCHBAR32( |
| 2652 | IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2653 | } |
| 2654 | FOR_ALL_LANES { |
| 2655 | struct run rn; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2656 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 2657 | stats[timC] = !!(raw_stats[timC] |
| 2658 | & (1 << lane)); |
| 2659 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2660 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2661 | rn = get_longest_zero_run(stats, MAX_TIMC + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2662 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2663 | printk(BIOS_EMERG, |
| 2664 | "timC write discovery failed: " |
| 2665 | "%d, %d, %d\n", channel, |
| 2666 | slotrank, lane); |
| 2667 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2668 | return MAKE_ERR; |
| 2669 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2670 | printram("timC: %d, %d, %d: " |
| 2671 | "0x%02x-0x%02x-0x%02x, " |
| 2672 | "0x%02x-0x%02x\n", channel, slotrank, |
| 2673 | i, rn.start, rn.middle, rn.end, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2674 | rn.start + ctrl->timC_offset[i], |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2675 | rn.end - ctrl->timC_offset[i]); |
| 2676 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2677 | lower[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2678 | MAX(rn.start + ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2679 | lower[channel][slotrank][lane]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2680 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2681 | upper[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2682 | MIN(rn.end - ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2683 | upper[channel][slotrank][lane]); |
| 2684 | |
| 2685 | } |
| 2686 | } |
| 2687 | } |
| 2688 | } |
| 2689 | |
| 2690 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2691 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2692 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2693 | udelay(2); |
| 2694 | } |
| 2695 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2696 | /* |
| 2697 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2698 | * FIXME: This must only be done on Ivy Bridge. |
| 2699 | */ |
| 2700 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2701 | |
| 2702 | printram("CPB\n"); |
| 2703 | |
| 2704 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2705 | printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2706 | (lower[channel][slotrank][lane] + |
| 2707 | upper[channel][slotrank][lane]) / 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2708 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2709 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2710 | (lower[channel][slotrank][lane] + |
| 2711 | upper[channel][slotrank][lane]) / 2; |
| 2712 | } |
| 2713 | FOR_ALL_POPULATED_CHANNELS { |
| 2714 | program_timings(ctrl, channel); |
| 2715 | } |
| 2716 | return 0; |
| 2717 | } |
| 2718 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2719 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2720 | { |
| 2721 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2722 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2723 | |
| 2724 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2725 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2726 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2727 | FOR_ALL_LANES mat = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2728 | MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2729 | printram("normalize %d, %d, %d: mat %d\n", |
| 2730 | channel, slotrank, lane, mat); |
| 2731 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2732 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2733 | printram("normalize %d, %d, %d: delta %d\n", |
| 2734 | channel, slotrank, lane, delta); |
| 2735 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2736 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2737 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2738 | } |
| 2739 | |
| 2740 | FOR_ALL_POPULATED_CHANNELS { |
| 2741 | program_timings(ctrl, channel); |
| 2742 | } |
| 2743 | } |
| 2744 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2745 | int channel_test(ramctr_timing *ctrl) |
| 2746 | { |
| 2747 | int channel, slotrank, lane; |
| 2748 | |
| 2749 | slotrank = 0; |
| 2750 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2751 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2752 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2753 | return MAKE_ERR; |
| 2754 | } |
| 2755 | FOR_ALL_POPULATED_CHANNELS { |
| 2756 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2757 | } |
| 2758 | |
| 2759 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 2760 | FOR_ALL_CHANNELS |
| 2761 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 2762 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2763 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 2764 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2765 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2766 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2767 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2768 | iosav_write_memory_test_sequence(ctrl, channel, slotrank); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2769 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2770 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2771 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2772 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2773 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2774 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2775 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2776 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 2777 | channel, slotrank, lane); |
| 2778 | return MAKE_ERR; |
| 2779 | } |
| 2780 | } |
| 2781 | return 0; |
| 2782 | } |
| 2783 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2784 | void channel_scrub(ramctr_timing *ctrl) |
| 2785 | { |
| 2786 | int channel, slotrank, row, rowsize; |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2787 | u8 bank; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2788 | |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2789 | FOR_ALL_POPULATED_CHANNELS { |
| 2790 | wait_for_iosav(channel); |
| 2791 | fill_pattern0(ctrl, channel, 0, 0); |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2792 | } |
| 2793 | |
| 2794 | /* |
| 2795 | * During runtime the "scrubber" will periodically scan through the memory in the |
| 2796 | * physical address space, to identify and fix CRC errors. |
| 2797 | * The following loops writes to every DRAM address, setting the ECC bits to the |
| 2798 | * correct value. A read from this location will no longer return a CRC error, |
| 2799 | * except when a bit has toggled due to external events. |
Angel Pons | 3b9d3e9 | 2020-11-11 19:10:39 +0100 | [diff] [blame] | 2800 | * The same could be achieved by writing to the physical memory map, but it's |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2801 | * much more difficult due to SMM remapping, ME stolen memory, GFX stolen memory, |
| 2802 | * and firmware running in x86_32. |
| 2803 | */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2804 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2805 | rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2806 | for (bank = 0; bank < 8; bank++) { |
| 2807 | for (row = 0; row < rowsize; row += 16) { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2808 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2809 | u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); |
| 2810 | const struct iosav_ssq sequence[] = { |
| 2811 | /* |
| 2812 | * DRAM command ACT |
| 2813 | * Opens the row for writing. |
| 2814 | */ |
| 2815 | [0] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2816 | .sp_cmd_ctrl = { |
| 2817 | .command = IOSAV_ACT, |
| 2818 | .ranksel_ap = 1, |
| 2819 | }, |
| 2820 | .subseq_ctrl = { |
| 2821 | .cmd_executions = 1, |
| 2822 | .cmd_delay_gap = gap, |
| 2823 | .post_ssq_wait = ctrl->tRCD, |
| 2824 | .data_direction = SSQ_NA, |
| 2825 | }, |
| 2826 | .sp_cmd_addr = { |
| 2827 | .address = row, |
| 2828 | .rowbits = 6, |
| 2829 | .bank = bank, |
| 2830 | .rank = slotrank, |
| 2831 | }, |
| 2832 | .addr_update = { |
| 2833 | .inc_addr_1 = 1, |
| 2834 | .addr_wrap = 18, |
| 2835 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2836 | }, |
| 2837 | /* |
| 2838 | * DRAM command WR |
| 2839 | * Writes (128 + 1) * 8 (burst length) * 8 (bus width) |
| 2840 | * bytes. |
| 2841 | */ |
| 2842 | [1] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2843 | .sp_cmd_ctrl = { |
| 2844 | .command = IOSAV_WR, |
| 2845 | .ranksel_ap = 1, |
| 2846 | }, |
| 2847 | .subseq_ctrl = { |
| 2848 | .cmd_executions = 129, |
| 2849 | .cmd_delay_gap = 4, |
| 2850 | .post_ssq_wait = ctrl->tWTR + |
| 2851 | ctrl->CWL + 8, |
| 2852 | .data_direction = SSQ_WR, |
| 2853 | }, |
| 2854 | .sp_cmd_addr = { |
| 2855 | .address = row, |
| 2856 | .rowbits = 0, |
| 2857 | .bank = bank, |
| 2858 | .rank = slotrank, |
| 2859 | }, |
| 2860 | .addr_update = { |
| 2861 | .inc_addr_8 = 1, |
| 2862 | .addr_wrap = 9, |
| 2863 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2864 | }, |
| 2865 | /* |
| 2866 | * DRAM command PRE |
| 2867 | * Closes the row. |
| 2868 | */ |
| 2869 | [2] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2870 | .sp_cmd_ctrl = { |
| 2871 | .command = IOSAV_PRE, |
| 2872 | .ranksel_ap = 1, |
| 2873 | }, |
| 2874 | .subseq_ctrl = { |
| 2875 | .cmd_executions = 1, |
| 2876 | .cmd_delay_gap = 4, |
| 2877 | .post_ssq_wait = ctrl->tRP, |
| 2878 | .data_direction = SSQ_NA, |
| 2879 | }, |
| 2880 | .sp_cmd_addr = { |
| 2881 | .address = 0, |
| 2882 | .rowbits = 6, |
| 2883 | .bank = bank, |
| 2884 | .rank = slotrank, |
| 2885 | }, |
| 2886 | .addr_update = { |
| 2887 | .addr_wrap = 18, |
| 2888 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2889 | }, |
| 2890 | }; |
| 2891 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2892 | |
| 2893 | /* Execute command queue */ |
| 2894 | iosav_run_queue(channel, 16, 0); |
| 2895 | |
| 2896 | wait_for_iosav(channel); |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2897 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2898 | } |
| 2899 | } |
| 2900 | } |
| 2901 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2902 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2903 | { |
| 2904 | int channel; |
| 2905 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2906 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2907 | static u32 seeds[NUM_CHANNELS][3] = { |
| 2908 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 2909 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 2910 | }; |
| 2911 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2912 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~(1 << 28); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2913 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 2914 | MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; |
| 2915 | MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2916 | } |
| 2917 | } |
| 2918 | |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 2919 | void set_wmm_behavior(const u32 cpu) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2920 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2921 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2922 | MCHBAR32(SC_WDBWM) = 0x141d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2923 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2924 | MCHBAR32(SC_WDBWM) = 0x551d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2925 | } |
| 2926 | } |
| 2927 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2928 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2929 | { |
| 2930 | int channel; |
| 2931 | |
| 2932 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2933 | /* Always drive command bus */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2934 | MCHBAR32_OR(TC_RAP_ch(channel), 1 << 29); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2935 | } |
| 2936 | |
| 2937 | udelay(1); |
| 2938 | |
| 2939 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2940 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2941 | } |
| 2942 | } |
| 2943 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2944 | void set_read_write_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2945 | { |
| 2946 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 2947 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2948 | FOR_ALL_POPULATED_CHANNELS { |
| 2949 | u32 b20, b4_8_12; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2950 | int min_pi = 10000; |
| 2951 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2952 | |
| 2953 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2954 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 2955 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2956 | } |
| 2957 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2958 | b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2959 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2960 | b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2961 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 2962 | dram_odt_stretch(ctrl, channel); |
| 2963 | |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2964 | MCHBAR32(TC_RWP_ch(channel)) = (1 << 27) | (2 << 24) | (b20 << 20) | |
Felix Held | 2463aa9 | 2018-07-29 21:37:55 +0200 | [diff] [blame] | 2965 | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2966 | } |
| 2967 | } |
| 2968 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2969 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2970 | { |
| 2971 | int channel; |
| 2972 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2973 | MCHBAR32(MC_INIT_STATE_ch(channel)) = (1 << 12) | ctrl->rankmap[channel]; |
| 2974 | MCHBAR32_AND(TC_RAP_ch(channel), ~(1 << 29)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2975 | } |
| 2976 | } |
| 2977 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2978 | /* Encode the watermark latencies in a suitable format for graphics drivers consumption */ |
| 2979 | static int encode_wm(int ns) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2980 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2981 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2982 | } |
| 2983 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2984 | /* FIXME: values in this function should be hardware revision-dependent */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2985 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2986 | { |
Angel Pons | b50ca57 | 2020-11-11 19:07:20 +0100 | [diff] [blame] | 2987 | const bool is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 2988 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2989 | int channel; |
| 2990 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 2991 | int t3_ns; |
| 2992 | u32 r32; |
| 2993 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2994 | /* FIXME: This register only exists on Ivy Bridge */ |
| 2995 | MCHBAR32(WMM_READ_CONFIG) = 0x46; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2996 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 2997 | FOR_ALL_CHANNELS |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2998 | MCHBAR32_AND_OR(TC_OTHP_ch(channel), ~(3 << 12), 1 << 12); |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 2999 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3000 | if (is_mobile) |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3001 | /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3002 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3003 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3004 | /* APD - PPD, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3005 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3006 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3007 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3008 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3009 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3010 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK |
| 3011 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3012 | |
| 3013 | FOR_ALL_CHANNELS { |
| 3014 | switch (ctrl->rankmap[channel]) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3015 | /* Unpopulated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3016 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3017 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3018 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3019 | /* Only single-ranked dimms */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3020 | case 1: |
| 3021 | case 4: |
| 3022 | case 5: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3023 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3024 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3025 | /* Dual-ranked dimms present */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3026 | default: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3027 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3028 | break; |
| 3029 | } |
| 3030 | } |
| 3031 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3032 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3033 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3034 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3035 | |
| 3036 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3037 | MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3038 | |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3039 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); |
| 3040 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3041 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3042 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3043 | /* Find a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3044 | FOR_ALL_POPULATED_CHANNELS |
| 3045 | break; |
| 3046 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3047 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 3048 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3049 | if (r32 & (1 << 17)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3050 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3051 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3052 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3053 | if (!(r32 & (1 << 17))) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3054 | t1_ns += 500; |
| 3055 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3056 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3057 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3058 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3059 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3060 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3061 | t3_ns = 500; |
| 3062 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3063 | |
| 3064 | /* The graphics driver will use these watermark values */ |
| 3065 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3066 | MCHBAR32_AND_OR(SSKPD, ~0x3f3f3f3f, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3067 | ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | |
| 3068 | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3069 | } |
| 3070 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3071 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3072 | { |
| 3073 | int channel, slotrank, lane; |
| 3074 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3075 | FOR_ALL_POPULATED_CHANNELS { |
| 3076 | MCHBAR32(TC_RAP_ch(channel)) = |
| 3077 | (ctrl->tRRD << 0) |
| 3078 | | (ctrl->tRTP << 4) |
| 3079 | | (ctrl->tCKE << 8) |
| 3080 | | (ctrl->tWTR << 12) |
| 3081 | | (ctrl->tFAW << 16) |
| 3082 | | (ctrl->tWR << 24) |
| 3083 | | (ctrl->cmd_stretch[channel] << 30); |
| 3084 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3085 | |
| 3086 | udelay(1); |
| 3087 | |
| 3088 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3089 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3090 | } |
| 3091 | |
| 3092 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3093 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3094 | } |
| 3095 | |
| 3096 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3097 | MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3098 | |
| 3099 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3100 | udelay(1); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3101 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3102 | } |
| 3103 | |
| 3104 | printram("CPE\n"); |
| 3105 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3106 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 3107 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3108 | |
| 3109 | printram("CP5b\n"); |
| 3110 | |
| 3111 | FOR_ALL_POPULATED_CHANNELS { |
| 3112 | program_timings(ctrl, channel); |
| 3113 | } |
| 3114 | |
| 3115 | u32 reg, addr; |
| 3116 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3117 | /* Poll for RCOMP */ |
| 3118 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 3119 | ; |
| 3120 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3121 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3122 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3123 | } while ((reg & 0x14) == 0); |
| 3124 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3125 | /* Set state of memory controller */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3126 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3127 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3128 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3129 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3130 | udelay(500); |
| 3131 | |
| 3132 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3133 | /* Set valid rank CKE */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3134 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3135 | reg = (reg & ~0x0f) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3136 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3137 | MCHBAR32(addr) = reg; |
| 3138 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3139 | /* Wait 10ns for ranks to settle */ |
| 3140 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3141 | |
| 3142 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 3143 | MCHBAR32(addr) = reg; |
| 3144 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3145 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3146 | write_reset(ctrl); |
| 3147 | } |
| 3148 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3149 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3150 | dram_mrscommands(ctrl); |
| 3151 | |
| 3152 | printram("CP5c\n"); |
| 3153 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3154 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3155 | |
| 3156 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3157 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3158 | udelay(2); |
| 3159 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3160 | } |