Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Iru Cai | 3364203 | 2019-06-11 14:24:43 +0800 | [diff] [blame] | 4 | #include <console/usb.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <string.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <cbmem.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | #include <cbfs.h> |
Elyes HAOUAS | 82d4642 | 2019-04-28 18:01:48 +0200 | [diff] [blame] | 8 | #include <cf9_reset.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include <ip_checksum.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 10 | #include <memory_info.h> |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 11 | #include <mrc_cache.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 12 | #include <device/pci_def.h> |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 14 | #include <device/dram/ddr3.h> |
| 15 | #include <smbios.h> |
| 16 | #include <spd.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 17 | #include <security/vboot/vboot_common.h> |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 18 | #include <commonlib/region.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | #include "raminit.h" |
| 20 | #include "pei_data.h" |
| 21 | #include "haswell.h" |
| 22 | |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 23 | #define MRC_CACHE_VERSION 1 |
| 24 | |
Aaron Durbin | 2ad1dba | 2013-02-07 00:51:18 -0600 | [diff] [blame] | 25 | void save_mrc_data(struct pei_data *pei_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | /* Save the MRC S3 restore data to cbmem */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 28 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, |
| 29 | pei_data->mrc_output_len); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | } |
| 31 | |
| 32 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 33 | { |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 34 | size_t mrc_size; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 36 | /* Preset just in case there is an error */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | pei_data->mrc_input = NULL; |
| 38 | pei_data->mrc_input_len = 0; |
| 39 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 40 | pei_data->mrc_input = |
| 41 | mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 42 | MRC_CACHE_VERSION, |
| 43 | &mrc_size); |
| 44 | if (!pei_data->mrc_input) |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 45 | /* Error message printed in find_current_mrc_cache */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 46 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 48 | pei_data->mrc_input_len = mrc_size; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 49 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 50 | printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__, |
| 51 | pei_data->mrc_input, mrc_size); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | } |
| 53 | |
Angel Pons | 0117e4e | 2020-10-13 23:34:27 +0200 | [diff] [blame] | 54 | static const char *const ecc_decoder[] = { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | "inactive", |
| 56 | "active on IO", |
| 57 | "disabled on IO", |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 58 | "active", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 59 | }; |
| 60 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 61 | /* Print out the memory controller configuration, as per the values in its registers. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | static void report_memory_config(void) |
| 63 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 64 | u32 addr_decoder_common, addr_decode_chan[2]; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | int i; |
| 66 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 67 | addr_decoder_common = MCHBAR32(MAD_CHNL); |
Angel Pons | 6791ad2 | 2020-10-13 21:44:08 +0200 | [diff] [blame] | 68 | addr_decode_chan[0] = MCHBAR32(MAD_DIMM(0)); |
| 69 | addr_decode_chan[1] = MCHBAR32(MAD_DIMM(1)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 70 | |
| 71 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 72 | (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); |
| 73 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 75 | (addr_decoder_common >> 0) & 3, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 76 | (addr_decoder_common >> 2) & 3, |
| 77 | (addr_decoder_common >> 4) & 3); |
| 78 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 79 | for (i = 0; i < ARRAY_SIZE(addr_decode_chan); i++) { |
| 80 | u32 ch_conf = addr_decode_chan[i]; |
| 81 | |
| 82 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); |
| 83 | printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 84 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 85 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 86 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 87 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 88 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 89 | |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 90 | printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 91 | ((ch_conf >> 0) & 0xff) * 256, |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 92 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 93 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 94 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 95 | |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 96 | printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 97 | ((ch_conf >> 8) & 0xff) * 256, |
Ryan Salsamendi | dab81a4 | 2017-06-30 17:36:41 -0700 | [diff] [blame] | 98 | ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 99 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 100 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | /** |
| 105 | * Find PEI executable in coreboot filesystem and execute it. |
| 106 | * |
| 107 | * @param pei_data: configuration data for UEFI PEI reference code |
| 108 | */ |
| 109 | void sdram_initialize(struct pei_data *pei_data) |
| 110 | { |
Angel Pons | 1ca6b53 | 2020-10-13 23:43:00 +0200 | [diff] [blame] | 111 | int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); |
| 112 | |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 113 | uint32_t type = CBFS_TYPE_MRC; |
| 114 | struct cbfsf f; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 115 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 117 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 118 | /* Do not pass MRC data in for recovery mode boot, always pass it in for S3 resume */ |
Julius Werner | 29fbfcc | 2020-03-02 15:54:43 -0800 | [diff] [blame] | 119 | if (!(CONFIG(HASWELL_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) |
| 120 | || pei_data->boot_mode == 2) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 121 | prepare_mrc_cache(pei_data); |
| 122 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 123 | /* If MRC data is not found, we cannot continue S3 resume */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
Duncan Laurie | 727b545 | 2013-08-08 16:28:41 -0700 | [diff] [blame] | 125 | post_code(POST_RESUME_FAILURE); |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 126 | printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); |
Elyes HAOUAS | 82d4642 | 2019-04-28 18:01:48 +0200 | [diff] [blame] | 127 | system_reset(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | /* Pass console handler in pei_data */ |
Kyösti Mälkki | 657e0be | 2014-02-04 19:03:57 +0200 | [diff] [blame] | 131 | pei_data->tx_byte = do_putchar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 133 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 134 | * Locate and call UEFI System Agent binary. The binary needs to be at a fixed offset |
| 135 | * in the flash and can therefore only reside in the COREBOOT fmap region. |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 136 | */ |
| 137 | if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) |
| 138 | die("mrc.bin not found!"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 139 | |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 140 | /* We don't care about leaking the mapping */ |
Angel Pons | 1ca6b53 | 2020-10-13 23:43:00 +0200 | [diff] [blame] | 141 | entry = rdev_mmap_full(&f.data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | if (entry) { |
Angel Pons | 1ca6b53 | 2020-10-13 23:43:00 +0200 | [diff] [blame] | 143 | int rv = entry(pei_data); |
Iru Cai | 3364203 | 2019-06-11 14:24:43 +0800 | [diff] [blame] | 144 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 145 | /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ |
Iru Cai | 3364203 | 2019-06-11 14:24:43 +0800 | [diff] [blame] | 146 | if (CONFIG(USBDEBUG_IN_PRE_RAM)) |
| 147 | usbdebug_hw_init(true); |
| 148 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 149 | if (rv) { |
| 150 | switch (rv) { |
| 151 | case -1: |
| 152 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 153 | break; |
| 154 | case -2: |
| 155 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 156 | break; |
| 157 | default: |
| 158 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 159 | } |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 160 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 161 | "Nonzero MRC return value.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 162 | } |
| 163 | } else { |
| 164 | die("UEFI PEI System Agent not found.\n"); |
| 165 | } |
| 166 | |
Angel Pons | 7f454e4 | 2020-10-13 23:49:03 +0200 | [diff] [blame] | 167 | /* Print the MRC version after executing the UEFI PEI stage */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 168 | u32 version = MCHBAR32(MRC_REVISION); |
Angel Pons | 7f454e4 | 2020-10-13 23:49:03 +0200 | [diff] [blame] | 169 | printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", |
| 170 | (version >> 24) & 0xff, (version >> 16) & 0xff, |
| 171 | (version >> 8) & 0xff, (version >> 0) & 0xff); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 172 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 173 | report_memory_config(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 174 | } |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 175 | |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 176 | static bool nb_supports_ecc(const uint32_t capid0_a) |
| 177 | { |
| 178 | return !(capid0_a & CAPID_ECCDIS); |
| 179 | } |
| 180 | |
| 181 | static uint16_t nb_slots_per_channel(const uint32_t capid0_a) |
| 182 | { |
| 183 | return !(capid0_a & CAPID_DDPCD) + 1; |
| 184 | } |
| 185 | |
| 186 | static uint16_t nb_number_of_channels(const uint32_t capid0_a) |
| 187 | { |
| 188 | return !(capid0_a & CAPID_PDCD) + 1; |
| 189 | } |
| 190 | |
| 191 | static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) |
| 192 | { |
| 193 | uint32_t ddrsz; |
| 194 | |
| 195 | /* Values from documentation, which assume two DIMMs per channel */ |
| 196 | switch (CAPID_DDRSZ(capid0_a)) { |
| 197 | case 1: |
| 198 | ddrsz = 8192; |
| 199 | break; |
| 200 | case 2: |
| 201 | ddrsz = 2048; |
| 202 | break; |
| 203 | case 3: |
| 204 | ddrsz = 512; |
| 205 | break; |
| 206 | default: |
| 207 | ddrsz = 16384; |
| 208 | break; |
| 209 | } |
| 210 | |
| 211 | /* Account for the maximum number of DIMMs per channel */ |
| 212 | return (ddrsz / 2) * nb_slots_per_channel(capid0_a); |
| 213 | } |
| 214 | |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 215 | void setup_sdram_meminfo(struct pei_data *pei_data) |
| 216 | { |
Elyes HAOUAS | ce83f31 | 2019-05-20 18:31:38 +0200 | [diff] [blame] | 217 | u32 addr_decode_ch[2]; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 218 | struct memory_info *mem_info; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 219 | struct dimm_info *dimm; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 220 | int ddr_frequency, dimm_size, ch, d_num; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 221 | int dimm_cnt = 0; |
| 222 | |
| 223 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); |
Nico Huber | acac02d | 2017-06-20 14:49:04 +0200 | [diff] [blame] | 224 | if (!mem_info) |
| 225 | die("Failed to add memory info to CBMEM.\n"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 226 | |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 227 | memset(mem_info, 0, sizeof(struct memory_info)); |
| 228 | |
Angel Pons | 6791ad2 | 2020-10-13 21:44:08 +0200 | [diff] [blame] | 229 | addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); |
| 230 | addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 231 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 232 | ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 233 | |
| 234 | for (ch = 0; ch < ARRAY_SIZE(addr_decode_ch); ch++) { |
| 235 | u32 ch_conf = addr_decode_ch[ch]; |
| 236 | /* DIMMs A/B */ |
| 237 | for (d_num = 0; d_num < 2; d_num++) { |
| 238 | dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; |
| 239 | if (dimm_size) { |
| 240 | dimm = &mem_info->dimm[dimm_cnt]; |
| 241 | dimm->dimm_size = dimm_size; |
| 242 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
| 243 | dimm->ddr_frequency = ddr_frequency; |
| 244 | dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); |
| 245 | dimm->channel_num = ch; |
| 246 | dimm->dimm_num = d_num; |
| 247 | dimm->bank_locator = ch * 2; |
| 248 | memcpy(dimm->serial, |
| 249 | &pei_data->spd_data[dimm_cnt][SPD_DIMM_SERIAL_NUM], |
| 250 | SPD_DIMM_SERIAL_LEN); |
| 251 | memcpy(dimm->module_part_number, |
| 252 | &pei_data->spd_data[dimm_cnt][SPD_DIMM_PART_NUM], |
| 253 | SPD_DIMM_PART_LEN); |
| 254 | dimm->mod_id = |
| 255 | (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 256 | (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xff); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 257 | dimm->mod_type = SPD_SODIMM; |
Elyes HAOUAS | 7d964ae | 2020-07-19 09:19:59 +0200 | [diff] [blame] | 258 | dimm->bus_width = MEMORY_BUS_WIDTH_64; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 259 | dimm_cnt++; |
| 260 | } |
| 261 | } |
| 262 | } |
| 263 | mem_info->dimm_cnt = dimm_cnt; |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 264 | |
| 265 | const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 266 | |
| 267 | const uint16_t channels = nb_number_of_channels(capid0_a); |
| 268 | |
| 269 | mem_info->ecc_capable = nb_supports_ecc(capid0_a); |
| 270 | mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); |
| 271 | mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 272 | } |