Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 3 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
| 4 | * Copyright (C) 2011 Stefan Tauner |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 5 | * |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but without any warranty; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* This file is derived from the flashrom project. */ |
| 18 | #include <stdint.h> |
| 19 | #include <stdlib.h> |
| 20 | #include <string.h> |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 21 | #include <bootstate.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 22 | #include <delay.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <console/console.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 25 | #include <device/pci_ids.h> |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 26 | #include <device/pci.h> |
| 27 | #include <spi_flash.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 28 | |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 29 | #include <spi-generic.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 30 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 31 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 32 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 33 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 34 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 35 | |
| 36 | |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 37 | #ifdef __SMM__ |
Kyösti Mälkki | 54d6abd | 2013-06-19 23:05:00 +0300 | [diff] [blame] | 38 | #include <arch/pci_mmio_cfg.h> |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 39 | #define pci_read_config_byte(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 40 | *(targ) = pci_read_config8(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 41 | #define pci_read_config_word(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 42 | *(targ) = pci_read_config16(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 43 | #define pci_read_config_dword(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 44 | *(targ) = pci_read_config32(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 45 | #define pci_write_config_byte(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 46 | pci_write_config8(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 47 | #define pci_write_config_word(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 48 | pci_write_config16(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 49 | #define pci_write_config_dword(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 50 | pci_write_config32(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 51 | #else /* !__SMM__ */ |
| 52 | #include <device/device.h> |
| 53 | #include <device/pci.h> |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 54 | #define pci_read_config_byte(dev, reg, targ)\ |
| 55 | *(targ) = pci_read_config8(dev, reg) |
| 56 | #define pci_read_config_word(dev, reg, targ)\ |
| 57 | *(targ) = pci_read_config16(dev, reg) |
| 58 | #define pci_read_config_dword(dev, reg, targ)\ |
| 59 | *(targ) = pci_read_config32(dev, reg) |
| 60 | #define pci_write_config_byte(dev, reg, val)\ |
| 61 | pci_write_config8(dev, reg, val) |
| 62 | #define pci_write_config_word(dev, reg, val)\ |
| 63 | pci_write_config16(dev, reg, val) |
| 64 | #define pci_write_config_dword(dev, reg, val)\ |
| 65 | pci_write_config32(dev, reg, val) |
| 66 | #endif /* !__SMM__ */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 67 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 68 | static int spi_is_multichip(void); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 69 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 70 | typedef struct spi_slave ich_spi_slave; |
| 71 | |
| 72 | static int ichspi_lock = 0; |
| 73 | |
| 74 | typedef struct ich7_spi_regs { |
| 75 | uint16_t spis; |
| 76 | uint16_t spic; |
| 77 | uint32_t spia; |
| 78 | uint64_t spid[8]; |
| 79 | uint64_t _pad; |
| 80 | uint32_t bbar; |
| 81 | uint16_t preop; |
| 82 | uint16_t optype; |
| 83 | uint8_t opmenu[8]; |
| 84 | } __attribute__((packed)) ich7_spi_regs; |
| 85 | |
| 86 | typedef struct ich9_spi_regs { |
| 87 | uint32_t bfpr; |
| 88 | uint16_t hsfs; |
| 89 | uint16_t hsfc; |
| 90 | uint32_t faddr; |
| 91 | uint32_t _reserved0; |
| 92 | uint32_t fdata[16]; |
| 93 | uint32_t frap; |
| 94 | uint32_t freg[5]; |
| 95 | uint32_t _reserved1[3]; |
| 96 | uint32_t pr[5]; |
| 97 | uint32_t _reserved2[2]; |
| 98 | uint8_t ssfs; |
| 99 | uint8_t ssfc[3]; |
| 100 | uint16_t preop; |
| 101 | uint16_t optype; |
| 102 | uint8_t opmenu[8]; |
| 103 | uint32_t bbar; |
| 104 | uint8_t _reserved3[12]; |
| 105 | uint32_t fdoc; |
| 106 | uint32_t fdod; |
| 107 | uint8_t _reserved4[8]; |
| 108 | uint32_t afc; |
| 109 | uint32_t lvscc; |
| 110 | uint32_t uvscc; |
| 111 | uint8_t _reserved5[4]; |
| 112 | uint32_t fpb; |
| 113 | uint8_t _reserved6[28]; |
| 114 | uint32_t srdl; |
| 115 | uint32_t srdc; |
| 116 | uint32_t srd; |
| 117 | } __attribute__((packed)) ich9_spi_regs; |
| 118 | |
| 119 | typedef struct ich_spi_controller { |
| 120 | int locked; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 121 | uint32_t flmap0; |
| 122 | uint32_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 123 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 124 | ich9_spi_regs *ich9_spi; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 125 | uint8_t *opmenu; |
| 126 | int menubytes; |
| 127 | uint16_t *preop; |
| 128 | uint16_t *optype; |
| 129 | uint32_t *addr; |
| 130 | uint8_t *data; |
| 131 | unsigned databytes; |
| 132 | uint8_t *status; |
| 133 | uint16_t *control; |
| 134 | uint32_t *bbar; |
| 135 | } ich_spi_controller; |
| 136 | |
| 137 | static ich_spi_controller cntlr; |
| 138 | |
| 139 | enum { |
| 140 | SPIS_SCIP = 0x0001, |
| 141 | SPIS_GRANT = 0x0002, |
| 142 | SPIS_CDS = 0x0004, |
| 143 | SPIS_FCERR = 0x0008, |
| 144 | SSFS_AEL = 0x0010, |
| 145 | SPIS_LOCK = 0x8000, |
| 146 | SPIS_RESERVED_MASK = 0x7ff0, |
| 147 | SSFS_RESERVED_MASK = 0x7fe2 |
| 148 | }; |
| 149 | |
| 150 | enum { |
| 151 | SPIC_SCGO = 0x000002, |
| 152 | SPIC_ACS = 0x000004, |
| 153 | SPIC_SPOP = 0x000008, |
| 154 | SPIC_DBC = 0x003f00, |
| 155 | SPIC_DS = 0x004000, |
| 156 | SPIC_SME = 0x008000, |
| 157 | SSFC_SCF_MASK = 0x070000, |
| 158 | SSFC_RESERVED = 0xf80000 |
| 159 | }; |
| 160 | |
| 161 | enum { |
| 162 | HSFS_FDONE = 0x0001, |
| 163 | HSFS_FCERR = 0x0002, |
| 164 | HSFS_AEL = 0x0004, |
| 165 | HSFS_BERASE_MASK = 0x0018, |
| 166 | HSFS_BERASE_SHIFT = 3, |
| 167 | HSFS_SCIP = 0x0020, |
| 168 | HSFS_FDOPSS = 0x2000, |
| 169 | HSFS_FDV = 0x4000, |
| 170 | HSFS_FLOCKDN = 0x8000 |
| 171 | }; |
| 172 | |
| 173 | enum { |
| 174 | HSFC_FGO = 0x0001, |
| 175 | HSFC_FCYCLE_MASK = 0x0006, |
| 176 | HSFC_FCYCLE_SHIFT = 1, |
| 177 | HSFC_FDBC_MASK = 0x3f00, |
| 178 | HSFC_FDBC_SHIFT = 8, |
| 179 | HSFC_FSMIE = 0x8000 |
| 180 | }; |
| 181 | |
| 182 | enum { |
| 183 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 184 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 185 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 186 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 187 | }; |
| 188 | |
| 189 | #if CONFIG_DEBUG_SPI_FLASH |
| 190 | |
| 191 | static u8 readb_(const void *addr) |
| 192 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 193 | u8 v = read8(addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 194 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
| 195 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 196 | return v; |
| 197 | } |
| 198 | |
| 199 | static u16 readw_(const void *addr) |
| 200 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 201 | u16 v = read16(addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 202 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
| 203 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 204 | return v; |
| 205 | } |
| 206 | |
| 207 | static u32 readl_(const void *addr) |
| 208 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 209 | u32 v = read32(addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 210 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
| 211 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 212 | return v; |
| 213 | } |
| 214 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 215 | static void writeb_(u8 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 216 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 217 | write8(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 218 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
| 219 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 220 | } |
| 221 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 222 | static void writew_(u16 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 223 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 224 | write16(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 225 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
| 226 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 227 | } |
| 228 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 229 | static void writel_(u32 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 230 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 231 | write32(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 232 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
| 233 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 234 | } |
| 235 | |
| 236 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 237 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 238 | #define readb_(a) read8(a) |
| 239 | #define readw_(a) read16(a) |
| 240 | #define readl_(a) read32(a) |
| 241 | #define writeb_(val, addr) write8(addr, val) |
| 242 | #define writew_(val, addr) write16(addr, val) |
| 243 | #define writel_(val, addr) write32(addr, val) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 244 | |
| 245 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 246 | |
| 247 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 248 | { |
| 249 | const uint8_t *bvalue = value; |
| 250 | uint8_t *bdest = dest; |
| 251 | |
| 252 | while (size >= 4) { |
| 253 | writel_(*(const uint32_t *)bvalue, bdest); |
| 254 | bdest += 4; bvalue += 4; size -= 4; |
| 255 | } |
| 256 | while (size) { |
| 257 | writeb_(*bvalue, bdest); |
| 258 | bdest++; bvalue++; size--; |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | static void read_reg(const void *src, void *value, uint32_t size) |
| 263 | { |
| 264 | const uint8_t *bsrc = src; |
| 265 | uint8_t *bvalue = value; |
| 266 | |
| 267 | while (size >= 4) { |
| 268 | *(uint32_t *)bvalue = readl_(bsrc); |
| 269 | bsrc += 4; bvalue += 4; size -= 4; |
| 270 | } |
| 271 | while (size) { |
| 272 | *bvalue = readb_(bsrc); |
| 273 | bsrc++; bvalue++; size--; |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | static void ich_set_bbar(uint32_t minaddr) |
| 278 | { |
| 279 | const uint32_t bbar_mask = 0x00ffff00; |
| 280 | uint32_t ichspi_bbar; |
| 281 | |
| 282 | minaddr &= bbar_mask; |
| 283 | ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; |
| 284 | ichspi_bbar |= minaddr; |
| 285 | writel_(ichspi_bbar, cntlr.bbar); |
| 286 | } |
| 287 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 288 | void spi_init(void) |
| 289 | { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 290 | uint8_t *rcrb; /* Root Complex Register Block */ |
| 291 | uint32_t rcba; /* Root Complex Base Address */ |
| 292 | uint8_t bios_cntl; |
Stefan Reinauer | 0c32c97 | 2012-07-10 13:26:59 -0700 | [diff] [blame] | 293 | device_t dev; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 294 | ich9_spi_regs *ich9_spi; |
| 295 | uint16_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 296 | |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 297 | #ifdef __SMM__ |
| 298 | dev = PCI_DEV(0, 31, 0); |
| 299 | #else |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 300 | dev = dev_find_slot(0, PCI_DEVFN(31, 0)); |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 301 | #endif |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 302 | |
| 303 | pci_read_config_dword(dev, 0xf0, &rcba); |
| 304 | /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ |
| 305 | rcrb = (uint8_t *)(rcba & 0xffffc000); |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 306 | ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); |
| 307 | cntlr.ich9_spi = ich9_spi; |
| 308 | hsfs = readw_(&ich9_spi->hsfs); |
| 309 | ichspi_lock = hsfs & HSFS_FLOCKDN; |
| 310 | cntlr.hsfs = hsfs; |
| 311 | cntlr.opmenu = ich9_spi->opmenu; |
| 312 | cntlr.menubytes = sizeof(ich9_spi->opmenu); |
| 313 | cntlr.optype = &ich9_spi->optype; |
| 314 | cntlr.addr = &ich9_spi->faddr; |
| 315 | cntlr.data = (uint8_t *)ich9_spi->fdata; |
| 316 | cntlr.databytes = sizeof(ich9_spi->fdata); |
| 317 | cntlr.status = &ich9_spi->ssfs; |
| 318 | cntlr.control = (uint16_t *)ich9_spi->ssfc; |
| 319 | cntlr.bbar = &ich9_spi->bbar; |
| 320 | cntlr.preop = &ich9_spi->preop; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 321 | |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 322 | if (cntlr.hsfs & HSFS_FDV) |
| 323 | { |
| 324 | writel_ (4, &ich9_spi->fdoc); |
| 325 | cntlr.flmap0 = readl_(&ich9_spi->fdod); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 326 | } |
| 327 | |
| 328 | ich_set_bbar(0); |
| 329 | |
| 330 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 331 | pci_read_config_byte(dev, 0xdc, &bios_cntl); |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 332 | /* Deassert SMM BIOS Write Protect Disable. */ |
| 333 | bios_cntl &= ~(1 << 5); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 334 | pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); |
| 335 | } |
Aaron Durbin | 4d3de7e | 2015-09-02 17:34:04 -0500 | [diff] [blame] | 336 | |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 337 | static void spi_init_cb(void *unused) |
| 338 | { |
| 339 | spi_init(); |
| 340 | } |
| 341 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 342 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 343 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 344 | typedef struct spi_transaction { |
| 345 | const uint8_t *out; |
| 346 | uint32_t bytesout; |
| 347 | uint8_t *in; |
| 348 | uint32_t bytesin; |
| 349 | uint8_t type; |
| 350 | uint8_t opcode; |
| 351 | uint32_t offset; |
| 352 | } spi_transaction; |
| 353 | |
| 354 | static inline void spi_use_out(spi_transaction *trans, unsigned bytes) |
| 355 | { |
| 356 | trans->out += bytes; |
| 357 | trans->bytesout -= bytes; |
| 358 | } |
| 359 | |
| 360 | static inline void spi_use_in(spi_transaction *trans, unsigned bytes) |
| 361 | { |
| 362 | trans->in += bytes; |
| 363 | trans->bytesin -= bytes; |
| 364 | } |
| 365 | |
| 366 | static void spi_setup_type(spi_transaction *trans) |
| 367 | { |
| 368 | trans->type = 0xFF; |
| 369 | |
| 370 | /* Try to guess spi type from read/write sizes. */ |
| 371 | if (trans->bytesin == 0) { |
| 372 | if (trans->bytesout > 4) |
| 373 | /* |
| 374 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 375 | * a write data operation, which is accompanied by an |
| 376 | * address. |
| 377 | */ |
| 378 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 379 | else |
| 380 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 381 | return; |
| 382 | } |
| 383 | |
| 384 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 385 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 386 | return; |
| 387 | } |
| 388 | |
| 389 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 390 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 391 | } |
Duncan Laurie | 23b0053 | 2012-10-10 14:21:23 -0700 | [diff] [blame] | 392 | |
| 393 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 394 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 395 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 396 | --trans->bytesout; |
| 397 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 398 | } |
| 399 | |
| 400 | static int spi_setup_opcode(spi_transaction *trans) |
| 401 | { |
| 402 | uint16_t optypes; |
| 403 | uint8_t opmenu[cntlr.menubytes]; |
| 404 | |
| 405 | trans->opcode = trans->out[0]; |
| 406 | spi_use_out(trans, 1); |
| 407 | if (!ichspi_lock) { |
| 408 | /* The lock is off, so just use index 0. */ |
| 409 | writeb_(trans->opcode, cntlr.opmenu); |
| 410 | optypes = readw_(cntlr.optype); |
| 411 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
| 412 | writew_(optypes, cntlr.optype); |
| 413 | return 0; |
| 414 | } else { |
| 415 | /* The lock is on. See if what we need is on the menu. */ |
| 416 | uint8_t optype; |
| 417 | uint16_t opcode_index; |
| 418 | |
Duncan Laurie | a2f1b95 | 2012-08-27 11:10:43 -0700 | [diff] [blame] | 419 | /* Write Enable is handled as atomic prefix */ |
| 420 | if (trans->opcode == SPI_OPCODE_WREN) |
| 421 | return 0; |
| 422 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 423 | read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); |
| 424 | for (opcode_index = 0; opcode_index < cntlr.menubytes; |
| 425 | opcode_index++) { |
| 426 | if (opmenu[opcode_index] == trans->opcode) |
| 427 | break; |
| 428 | } |
| 429 | |
| 430 | if (opcode_index == cntlr.menubytes) { |
| 431 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 432 | trans->opcode); |
| 433 | return -1; |
| 434 | } |
| 435 | |
| 436 | optypes = readw_(cntlr.optype); |
| 437 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 438 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 439 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 440 | trans->bytesout >= 3) { |
| 441 | /* We guessed wrong earlier. Fix it up. */ |
| 442 | trans->type = optype; |
| 443 | } |
| 444 | if (optype != trans->type) { |
| 445 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 446 | optype); |
| 447 | return -1; |
| 448 | } |
| 449 | return opcode_index; |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | static int spi_setup_offset(spi_transaction *trans) |
| 454 | { |
| 455 | /* Separate the SPI address and data. */ |
| 456 | switch (trans->type) { |
| 457 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 458 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 459 | return 0; |
| 460 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 461 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 462 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 463 | ((uint32_t)trans->out[1] << 8) | |
| 464 | ((uint32_t)trans->out[2] << 0); |
| 465 | spi_use_out(trans, 3); |
| 466 | return 1; |
| 467 | default: |
| 468 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 469 | return -1; |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | /* |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 474 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 475 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 476 | * those bits back, which would cause resetting them. |
| 477 | * |
| 478 | * Return the last read status value on success or -1 on failure. |
| 479 | */ |
| 480 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 481 | { |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 482 | int timeout = 600000; /* This will result in 6 seconds */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 483 | u16 status = 0; |
| 484 | |
| 485 | while (timeout--) { |
| 486 | status = readw_(cntlr.status); |
| 487 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 488 | if (wait_til_set) |
| 489 | writew_((status & bitmask), cntlr.status); |
| 490 | return status; |
| 491 | } |
| 492 | udelay(10); |
| 493 | } |
| 494 | |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 495 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 496 | status, bitmask); |
| 497 | return -1; |
| 498 | } |
| 499 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 500 | static int spi_is_multichip (void) |
| 501 | { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 502 | if (!(cntlr.hsfs & HSFS_FDV)) |
| 503 | return 0; |
| 504 | return !!((cntlr.flmap0 >> 8) & 3); |
| 505 | } |
| 506 | |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 507 | unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) |
| 508 | { |
| 509 | return min(cntlr.databytes, buf_len); |
| 510 | } |
| 511 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 512 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 513 | size_t bytesout, void *din, size_t bytesin) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 514 | { |
| 515 | uint16_t control; |
| 516 | int16_t opcode_index; |
| 517 | int with_address; |
| 518 | int status; |
| 519 | |
| 520 | spi_transaction trans = { |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 521 | dout, bytesout, |
| 522 | din, bytesin, |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 523 | 0xff, 0xff, 0 |
| 524 | }; |
| 525 | |
| 526 | /* There has to always at least be an opcode. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 527 | if (!bytesout || !dout) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 528 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 529 | return -1; |
| 530 | } |
| 531 | /* Make sure if we read something we have a place to put it. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 532 | if (bytesin != 0 && !din) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 533 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 534 | return -1; |
| 535 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 536 | |
| 537 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 538 | return -1; |
| 539 | |
| 540 | writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); |
| 541 | |
| 542 | spi_setup_type(&trans); |
| 543 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 544 | return -1; |
| 545 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 546 | return -1; |
| 547 | |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 548 | if (trans.opcode == SPI_OPCODE_WREN) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 549 | /* |
| 550 | * Treat Write Enable as Atomic Pre-Op if possible |
| 551 | * in order to prevent the Management Engine from |
| 552 | * issuing a transaction between WREN and DATA. |
| 553 | */ |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 554 | if (!ichspi_lock) |
| 555 | writew_(trans.opcode, cntlr.preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 556 | return 0; |
| 557 | } |
| 558 | |
| 559 | /* Preset control fields */ |
| 560 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 561 | |
| 562 | /* Issue atomic preop cycle if needed */ |
| 563 | if (readw_(cntlr.preop)) |
| 564 | control |= SPIC_ACS; |
| 565 | |
| 566 | if (!trans.bytesout && !trans.bytesin) { |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 567 | /* SPI addresses are 24 bit only */ |
| 568 | if (with_address) |
| 569 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 570 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 571 | /* |
| 572 | * This is a 'no data' command (like Write Enable), its |
| 573 | * bitesout size was 1, decremented to zero while executing |
| 574 | * spi_setup_opcode() above. Tell the chip to send the |
| 575 | * command. |
| 576 | */ |
| 577 | writew_(control, cntlr.control); |
| 578 | |
| 579 | /* wait for the result */ |
| 580 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 581 | if (status == -1) |
| 582 | return -1; |
| 583 | |
| 584 | if (status & SPIS_FCERR) { |
| 585 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 586 | return -1; |
| 587 | } |
| 588 | |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | /* |
Paul Menzel | 9478297 | 2013-06-29 11:41:27 +0200 | [diff] [blame] | 593 | * Check if this is a write command attempting to transfer more bytes |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 594 | * than the controller can handle. Iterations for writes are not |
| 595 | * supported here because each SPI write command needs to be preceded |
| 596 | * and followed by other SPI commands, and this sequence is controlled |
| 597 | * by the SPI chip driver. |
| 598 | */ |
| 599 | if (trans.bytesout > cntlr.databytes) { |
| 600 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 601 | " spi_crop_chunk()?\n"); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 602 | return -1; |
| 603 | } |
| 604 | |
| 605 | /* |
| 606 | * Read or write up to databytes bytes at a time until everything has |
| 607 | * been sent. |
| 608 | */ |
| 609 | while (trans.bytesout || trans.bytesin) { |
| 610 | uint32_t data_length; |
| 611 | |
| 612 | /* SPI addresses are 24 bit only */ |
| 613 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 614 | |
| 615 | if (trans.bytesout) |
| 616 | data_length = min(trans.bytesout, cntlr.databytes); |
| 617 | else |
| 618 | data_length = min(trans.bytesin, cntlr.databytes); |
| 619 | |
| 620 | /* Program data into FDATA0 to N */ |
| 621 | if (trans.bytesout) { |
| 622 | write_reg(trans.out, cntlr.data, data_length); |
| 623 | spi_use_out(&trans, data_length); |
| 624 | if (with_address) |
| 625 | trans.offset += data_length; |
| 626 | } |
| 627 | |
| 628 | /* Add proper control fields' values */ |
| 629 | control &= ~((cntlr.databytes - 1) << 8); |
| 630 | control |= SPIC_DS; |
| 631 | control |= (data_length - 1) << 8; |
| 632 | |
| 633 | /* write it */ |
| 634 | writew_(control, cntlr.control); |
| 635 | |
| 636 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 637 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 638 | if (status == -1) |
| 639 | return -1; |
| 640 | |
| 641 | if (status & SPIS_FCERR) { |
| 642 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 643 | return -1; |
| 644 | } |
| 645 | |
| 646 | if (trans.bytesin) { |
| 647 | read_reg(cntlr.data, trans.in, data_length); |
| 648 | spi_use_in(&trans, data_length); |
| 649 | if (with_address) |
| 650 | trans.offset += data_length; |
| 651 | } |
| 652 | } |
| 653 | |
| 654 | /* Clear atomic preop now that xfer is done */ |
| 655 | writew_(0, cntlr.preop); |
| 656 | |
| 657 | return 0; |
| 658 | } |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 659 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 660 | static const struct spi_ctrlr spi_ctrlr = { |
| 661 | .xfer = spi_ctrlr_xfer, |
| 662 | }; |
| 663 | |
| 664 | int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) |
| 665 | { |
| 666 | slave->bus = bus; |
| 667 | slave->cs = cs; |
| 668 | slave->ctrlr = &spi_ctrlr; |
| 669 | return 0; |
| 670 | } |
| 671 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 672 | /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ |
| 673 | static void ich_hwseq_set_addr(uint32_t addr) |
| 674 | { |
| 675 | uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; |
| 676 | writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); |
| 677 | } |
| 678 | |
| 679 | /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. |
| 680 | Resets all error flags in HSFS. |
| 681 | Returns 0 if the cycle completes successfully without errors within |
| 682 | timeout us, 1 on errors. */ |
| 683 | static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, |
| 684 | unsigned int len) |
| 685 | { |
| 686 | uint16_t hsfs; |
| 687 | uint32_t addr; |
| 688 | |
| 689 | timeout /= 8; /* scale timeout duration to counter */ |
| 690 | while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & |
| 691 | (HSFS_FDONE | HSFS_FCERR)) == 0) && |
| 692 | --timeout) { |
| 693 | udelay(8); |
| 694 | } |
| 695 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 696 | |
| 697 | if (!timeout) { |
| 698 | uint16_t hsfc; |
| 699 | addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; |
| 700 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 701 | printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " |
| 702 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 703 | addr, addr + len - 1, addr, len - 1, |
| 704 | hsfc, hsfs); |
| 705 | return 1; |
| 706 | } |
| 707 | |
| 708 | if (hsfs & HSFS_FCERR) { |
| 709 | uint16_t hsfc; |
| 710 | addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; |
| 711 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 712 | printk(BIOS_ERR, "Transaction error between offset 0x%08x and " |
| 713 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 714 | addr, addr + len - 1, addr, len - 1, |
| 715 | hsfc, hsfs); |
| 716 | return 1; |
| 717 | } |
| 718 | return 0; |
| 719 | } |
| 720 | |
| 721 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 722 | static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, |
| 723 | size_t len) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 724 | { |
| 725 | u32 start, end, erase_size; |
| 726 | int ret; |
| 727 | uint16_t hsfc; |
| 728 | uint16_t timeout = 1000 * 60; |
| 729 | |
| 730 | erase_size = flash->sector_size; |
| 731 | if (offset % erase_size || len % erase_size) { |
| 732 | printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); |
| 733 | return -1; |
| 734 | } |
| 735 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 736 | ret = spi_claim_bus(flash->spi); |
| 737 | if (ret) { |
| 738 | printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); |
| 739 | return ret; |
| 740 | } |
| 741 | |
| 742 | start = offset; |
| 743 | end = start + len; |
| 744 | |
| 745 | while (offset < end) { |
| 746 | /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ |
| 747 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 748 | |
| 749 | ich_hwseq_set_addr(offset); |
| 750 | |
| 751 | offset += erase_size; |
| 752 | |
| 753 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 754 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 755 | hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ |
| 756 | hsfc |= HSFC_FGO; /* start */ |
| 757 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
| 758 | if (ich_hwseq_wait_for_cycle_complete(timeout, len)) |
| 759 | { |
| 760 | printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); |
| 761 | ret = -1; |
| 762 | goto out; |
| 763 | } |
| 764 | } |
| 765 | |
| 766 | printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); |
| 767 | |
| 768 | out: |
| 769 | spi_release_bus(flash->spi); |
| 770 | return ret; |
| 771 | } |
| 772 | |
| 773 | static void ich_read_data(uint8_t *data, int len) |
| 774 | { |
| 775 | int i; |
| 776 | uint32_t temp32 = 0; |
| 777 | |
| 778 | for (i = 0; i < len; i++) { |
| 779 | if ((i % 4) == 0) |
| 780 | temp32 = readl_(cntlr.data + i); |
| 781 | |
| 782 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 783 | } |
| 784 | } |
| 785 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 786 | static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, |
| 787 | void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 788 | { |
| 789 | uint16_t hsfc; |
| 790 | uint16_t timeout = 100 * 60; |
| 791 | uint8_t block_len; |
| 792 | |
| 793 | if (addr + len > flash->size) { |
| 794 | printk (BIOS_ERR, |
| 795 | "Attempt to read %x-%x which is out of chip\n", |
| 796 | (unsigned) addr, |
| 797 | (unsigned) addr+(unsigned) len); |
| 798 | return -1; |
| 799 | } |
| 800 | |
| 801 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
| 802 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 803 | |
| 804 | while (len > 0) { |
| 805 | block_len = min(len, cntlr.databytes); |
| 806 | if (block_len > (~addr & 0xff)) |
| 807 | block_len = (~addr & 0xff) + 1; |
| 808 | ich_hwseq_set_addr(addr); |
| 809 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 810 | hsfc &= ~HSFC_FCYCLE; /* set read operation */ |
| 811 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 812 | /* set byte count */ |
| 813 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 814 | hsfc |= HSFC_FGO; /* start */ |
| 815 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
| 816 | |
| 817 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 818 | return 1; |
| 819 | ich_read_data(buf, block_len); |
| 820 | addr += block_len; |
| 821 | buf += block_len; |
| 822 | len -= block_len; |
| 823 | } |
| 824 | return 0; |
| 825 | } |
| 826 | |
| 827 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 828 | * |
| 829 | * Note that using len > flash->pgm->spi.max_data_write will trash the registers |
| 830 | * following the data registers. |
| 831 | */ |
| 832 | static void ich_fill_data(const uint8_t *data, int len) |
| 833 | { |
| 834 | uint32_t temp32 = 0; |
| 835 | int i; |
| 836 | |
| 837 | if (len <= 0) |
| 838 | return; |
| 839 | |
| 840 | for (i = 0; i < len; i++) { |
| 841 | if ((i % 4) == 0) |
| 842 | temp32 = 0; |
| 843 | |
| 844 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 845 | |
| 846 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
| 847 | writel_(temp32, cntlr.data + (i - (i % 4))); |
| 848 | } |
| 849 | i--; |
| 850 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
| 851 | writel_(temp32, cntlr.data + (i - (i % 4))); |
| 852 | } |
| 853 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 854 | static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, |
| 855 | const void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 856 | { |
| 857 | uint16_t hsfc; |
| 858 | uint16_t timeout = 100 * 60; |
| 859 | uint8_t block_len; |
| 860 | uint32_t start = addr; |
| 861 | |
| 862 | if (addr + len > flash->size) { |
| 863 | printk (BIOS_ERR, |
| 864 | "Attempt to write 0x%x-0x%x which is out of chip\n", |
| 865 | (unsigned)addr, (unsigned) (addr+len)); |
| 866 | return -1; |
| 867 | } |
| 868 | |
| 869 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
| 870 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 871 | |
| 872 | while (len > 0) { |
| 873 | block_len = min(len, cntlr.databytes); |
| 874 | if (block_len > (~addr & 0xff)) |
| 875 | block_len = (~addr & 0xff) + 1; |
| 876 | |
| 877 | ich_hwseq_set_addr(addr); |
| 878 | |
| 879 | ich_fill_data(buf, block_len); |
| 880 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 881 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 882 | hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ |
| 883 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 884 | /* set byte count */ |
| 885 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 886 | hsfc |= HSFC_FGO; /* start */ |
| 887 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
| 888 | |
| 889 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 890 | { |
| 891 | printk (BIOS_ERR, "SF: write failure at %x\n", |
| 892 | addr); |
| 893 | return -1; |
| 894 | } |
| 895 | addr += block_len; |
| 896 | buf += block_len; |
| 897 | len -= block_len; |
| 898 | } |
| 899 | printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", |
| 900 | (unsigned) (addr - start), start); |
| 901 | return 0; |
| 902 | } |
| 903 | |
| 904 | |
Furquan Shaikh | d2fb6ae | 2016-11-17 20:38:07 -0800 | [diff] [blame] | 905 | struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 906 | { |
| 907 | struct spi_flash *flash = NULL; |
| 908 | uint32_t flcomp; |
| 909 | |
Furquan Shaikh | d2fb6ae | 2016-11-17 20:38:07 -0800 | [diff] [blame] | 910 | /* |
| 911 | * Perform SPI flash probing only if: |
| 912 | * 1. spi_is_multichip returns 1 or |
| 913 | * 2. Specialized probing is forced by SPI flash driver. |
| 914 | */ |
| 915 | if (!spi_is_multichip() && !force) |
| 916 | return NULL; |
| 917 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 918 | flash = malloc(sizeof(*flash)); |
| 919 | if (!flash) { |
| 920 | printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); |
| 921 | return NULL; |
| 922 | } |
| 923 | |
| 924 | flash->spi = spi; |
| 925 | flash->name = "Opaque HW-sequencing"; |
| 926 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 927 | flash->internal_write = ich_hwseq_write; |
| 928 | flash->internal_erase = ich_hwseq_erase; |
| 929 | flash->internal_read = ich_hwseq_read; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 930 | ich_hwseq_set_addr (0); |
| 931 | switch ((cntlr.hsfs >> 3) & 3) |
| 932 | { |
| 933 | case 0: |
| 934 | flash->sector_size = 256; |
| 935 | break; |
| 936 | case 1: |
| 937 | flash->sector_size = 4096; |
| 938 | break; |
| 939 | case 2: |
| 940 | flash->sector_size = 8192; |
| 941 | break; |
| 942 | case 3: |
| 943 | flash->sector_size = 65536; |
| 944 | break; |
| 945 | } |
| 946 | |
| 947 | writel_ (0x1000, &cntlr.ich9_spi->fdoc); |
| 948 | flcomp = readl_(&cntlr.ich9_spi->fdod); |
| 949 | |
| 950 | flash->size = 1 << (19 + (flcomp & 7)); |
| 951 | |
| 952 | if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) |
| 953 | flash->size += 1 << (19 + ((flcomp >> 3) & 7)); |
| 954 | printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); |
| 955 | |
| 956 | return flash; |
| 957 | } |