Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Elyes HAOUAS | c27014b | 2019-06-23 11:11:53 +0200 | [diff] [blame] | 8 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include "haswell.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 11 | static bool peg_hidden[3]; |
| 12 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | static void haswell_setup_bars(void) |
| 14 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 16 | /* Set up all hardcoded northbridge BARs */ |
Angel Pons | f95b9b4 | 2021-01-20 01:10:48 +0100 | [diff] [blame] | 17 | pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); |
| 18 | pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0); |
| 19 | pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); |
| 20 | pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); |
| 21 | pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); |
| 22 | pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | |
Angel Pons | 6a2a514 | 2021-06-14 09:39:01 +0200 | [diff] [blame] | 24 | mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1); |
| 25 | mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1); |
| 26 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 28 | pci_write_config8(HOST_BRIDGE, PAM0, 0x30); |
| 29 | pci_write_config8(HOST_BRIDGE, PAM1, 0x33); |
| 30 | pci_write_config8(HOST_BRIDGE, PAM2, 0x33); |
| 31 | pci_write_config8(HOST_BRIDGE, PAM3, 0x33); |
| 32 | pci_write_config8(HOST_BRIDGE, PAM4, 0x33); |
| 33 | pci_write_config8(HOST_BRIDGE, PAM5, 0x33); |
| 34 | pci_write_config8(HOST_BRIDGE, PAM6, 0x33); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | |
| 36 | printk(BIOS_DEBUG, " done.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | } |
| 38 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 39 | static void haswell_setup_igd(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | { |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 41 | bool igd_enabled; |
| 42 | u16 ggc; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 44 | printk(BIOS_DEBUG, "Initializing IGD...\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 46 | igd_enabled = !!(pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 47 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 48 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 49 | ggc &= ~0x3f8; |
| 50 | if (igd_enabled) { |
| 51 | ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1); |
| 52 | ggc &= ~GGC_DISABLE_VGA_IO_DECODE; |
| 53 | } else { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 54 | ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | GGC_DISABLE_VGA_IO_DECODE; |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 55 | } |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 56 | pci_write_config16(HOST_BRIDGE, GGC, ggc); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 57 | |
| 58 | if (!igd_enabled) { |
| 59 | printk(BIOS_DEBUG, "IGD is disabled.\n"); |
| 60 | return; |
| 61 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
| 63 | /* Enable 256MB aperture */ |
Angel Pons | 2688607 | 2020-06-07 22:19:21 +0200 | [diff] [blame] | 64 | pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 65 | } |
| 66 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 67 | static void start_peg2_link_training(const pci_devfn_t dev) |
| 68 | { |
| 69 | u32 mask; |
| 70 | |
| 71 | switch (dev) { |
| 72 | case PCI_DEV(0, 1, 2): |
| 73 | mask = DEVEN_D1F2EN; |
| 74 | break; |
| 75 | case PCI_DEV(0, 1, 1): |
| 76 | mask = DEVEN_D1F1EN; |
| 77 | break; |
| 78 | case PCI_DEV(0, 1, 0): |
| 79 | mask = DEVEN_D1F0EN; |
| 80 | break; |
| 81 | default: |
| 82 | printk(BIOS_ERR, "Link training tried on a non-PEG device!\n"); |
| 83 | return; |
| 84 | } |
| 85 | |
| 86 | pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5); |
Chris Morgan | 2806ec9 | 2020-02-05 10:51:46 -0600 | [diff] [blame] | 87 | printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 88 | |
| 89 | /* |
Angel Pons | 84641c8 | 2020-08-29 02:52:09 +0200 | [diff] [blame] | 90 | * The MRC will perform PCI enumeration, and if it detects a VGA |
| 91 | * device in a PEG slot, it will disable the IGD and not reserve |
| 92 | * any memory for it. Since the memory map is locked by the time |
| 93 | * MRC finishes, the IGD can't be enabled afterwards. Wonderful. |
| 94 | * |
| 95 | * If one really wants to enable the Intel iGPU as primary, hide |
| 96 | * all PEG devices during MRC execution. This will trick the MRC |
| 97 | * into thinking there aren't any, and will enable the IGD. Note |
| 98 | * that PEG AFE settings will not be programmed, which may cause |
| 99 | * stability problems at higher PCIe link speeds. The most ideal |
| 100 | * way to fix this problem for good is to implement native init. |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 101 | */ |
Angel Pons | 84641c8 | 2020-08-29 02:52:09 +0200 | [diff] [blame] | 102 | if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) { |
| 103 | pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); |
| 104 | peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; |
| 105 | printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", |
| 106 | PCI_FUNC(PCI_DEV2DEVFN(dev))); |
| 107 | } |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | void haswell_unhide_peg(void) |
| 111 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 112 | u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 113 | |
| 114 | for (u8 fn = 0; fn <= 2; fn++) { |
| 115 | if (peg_hidden[fn]) { |
| 116 | deven |= DEVEN_D1F0EN >> fn; |
| 117 | peg_hidden[fn] = false; |
| 118 | printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn); |
| 119 | } |
| 120 | } |
| 121 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 122 | pci_write_config32(HOST_BRIDGE, DEVEN, deven); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | static void haswell_setup_peg(void) |
| 126 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 127 | u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 128 | |
| 129 | if (deven & DEVEN_D1F2EN) |
| 130 | start_peg2_link_training(PCI_DEV(0, 1, 2)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 131 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 132 | if (deven & DEVEN_D1F1EN) |
| 133 | start_peg2_link_training(PCI_DEV(0, 1, 1)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 134 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 135 | if (deven & DEVEN_D1F0EN) |
| 136 | start_peg2_link_training(PCI_DEV(0, 1, 0)); |
| 137 | } |
| 138 | |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 139 | static void haswell_setup_misc(void) |
| 140 | { |
| 141 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | |
| 143 | /* Erratum workarounds */ |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 144 | reg32 = mchbar_read32(SAPMCTL); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 145 | reg32 |= (1 << 9) | (1 << 10); |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 146 | mchbar_write32(SAPMCTL, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 147 | |
| 148 | /* Enable SA Clock Gating */ |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 149 | reg32 = mchbar_read32(SAPMCTL); |
| 150 | mchbar_write32(SAPMCTL, reg32 | 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 151 | |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 152 | reg32 = mchbar_read32(INTRDIRCTL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 153 | reg32 |= (1 << 4) | (1 << 5); |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 154 | mchbar_write32(INTRDIRCTL, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 155 | } |
| 156 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 157 | static void haswell_setup_iommu(void) |
| 158 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 159 | const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 160 | |
| 161 | if (capid0_a & VTD_DISABLE) |
| 162 | return; |
| 163 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 164 | /* Setup BARs: zeroize top 32 bits; set enable bit */ |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 165 | mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); |
| 166 | mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); |
| 167 | mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); |
| 168 | mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 169 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 170 | /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 171 | u32 reg32; |
Elyes Haouas | 9a83eae | 2022-12-03 13:31:38 +0100 | [diff] [blame] | 172 | reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS); |
| 173 | write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 174 | |
| 175 | /* Clear SPCAPCTRL */ |
Elyes Haouas | 9a83eae | 2022-12-03 13:31:38 +0100 | [diff] [blame] | 176 | reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS) & ~SPCAPCTRL; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 177 | |
| 178 | /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */ |
Elyes Haouas | 9a83eae | 2022-12-03 13:31:38 +0100 | [diff] [blame] | 179 | write32p(VTVC0_BASE_ADDRESS + ARCHDIS, |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 180 | reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); |
| 181 | } |
| 182 | |
Angel Pons | e816829 | 2020-07-03 11:42:22 +0200 | [diff] [blame] | 183 | void haswell_early_initialization(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 184 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 185 | /* Setup all BARs required for early PCIe and raminit */ |
| 186 | haswell_setup_bars(); |
| 187 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 188 | /* Setup IOMMU BARs */ |
| 189 | haswell_setup_iommu(); |
| 190 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 191 | haswell_setup_peg(); |
| 192 | haswell_setup_igd(); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 193 | |
| 194 | haswell_setup_misc(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 195 | } |