Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 21 | #include <device/pci_def.h> |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame^] | 22 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | #include <elog.h> |
| 24 | #include "haswell.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame^] | 26 | static bool peg_hidden[3]; |
| 27 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 28 | static void haswell_setup_bars(void) |
| 29 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 31 | /* Set up all hardcoded northbridge BARs */ |
| 32 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 33 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); |
| 34 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| 35 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 36 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
| 37 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | |
| 39 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 40 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 41 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 42 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 43 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 44 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 45 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 46 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 47 | |
| 48 | printk(BIOS_DEBUG, " done.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 49 | } |
| 50 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame^] | 51 | static void haswell_setup_igd(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | { |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 53 | bool igd_enabled; |
| 54 | u16 ggc; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | u8 reg8; |
| 56 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame^] | 57 | printk(BIOS_DEBUG, "Initializing IGD...\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 59 | igd_enabled = !!(pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) |
| 60 | & DEVEN_D2EN); |
| 61 | |
| 62 | ggc = pci_read_config16(PCI_DEV(0, 0, 0), GGC); |
| 63 | ggc &= ~0x3f8; |
| 64 | if (igd_enabled) { |
| 65 | ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1); |
| 66 | ggc &= ~GGC_DISABLE_VGA_IO_DECODE; |
| 67 | } else { |
| 68 | ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | |
| 69 | GGC_DISABLE_VGA_IO_DECODE; |
| 70 | } |
| 71 | pci_write_config16(PCI_DEV(0, 0, 0), GGC, ggc); |
| 72 | |
| 73 | if (!igd_enabled) { |
| 74 | printk(BIOS_DEBUG, "IGD is disabled.\n"); |
| 75 | return; |
| 76 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | |
| 78 | /* Enable 256MB aperture */ |
| 79 | reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); |
| 80 | reg8 &= ~0x06; |
| 81 | reg8 |= 0x02; |
| 82 | pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 83 | } |
| 84 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame^] | 85 | static void start_peg2_link_training(const pci_devfn_t dev) |
| 86 | { |
| 87 | u32 mask; |
| 88 | |
| 89 | switch (dev) { |
| 90 | case PCI_DEV(0, 1, 2): |
| 91 | mask = DEVEN_D1F2EN; |
| 92 | break; |
| 93 | case PCI_DEV(0, 1, 1): |
| 94 | mask = DEVEN_D1F1EN; |
| 95 | break; |
| 96 | case PCI_DEV(0, 1, 0): |
| 97 | mask = DEVEN_D1F0EN; |
| 98 | break; |
| 99 | default: |
| 100 | printk(BIOS_ERR, "Link training tried on a non-PEG device!\n"); |
| 101 | return; |
| 102 | } |
| 103 | |
| 104 | pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5); |
| 105 | printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev)); |
| 106 | |
| 107 | /* |
| 108 | * The PEG device is hidden while the MRC runs. This is because the |
| 109 | * MRC makes configurations that are not ideal if it sees a VGA |
| 110 | * device in a PEG slot, and it locks registers preventing changes |
| 111 | * to these configurations. |
| 112 | */ |
| 113 | pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0); |
| 114 | peg_hidden[PCI_FUNC(dev)] = true; |
| 115 | printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(dev)); |
| 116 | } |
| 117 | |
| 118 | void haswell_unhide_peg(void) |
| 119 | { |
| 120 | u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); |
| 121 | |
| 122 | for (u8 fn = 0; fn <= 2; fn++) { |
| 123 | if (peg_hidden[fn]) { |
| 124 | deven |= DEVEN_D1F0EN >> fn; |
| 125 | peg_hidden[fn] = false; |
| 126 | printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn); |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); |
| 131 | } |
| 132 | |
| 133 | static void haswell_setup_peg(void) |
| 134 | { |
| 135 | u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); |
| 136 | |
| 137 | if (deven & DEVEN_D1F2EN) |
| 138 | start_peg2_link_training(PCI_DEV(0, 1, 2)); |
| 139 | if (deven & DEVEN_D1F1EN) |
| 140 | start_peg2_link_training(PCI_DEV(0, 1, 1)); |
| 141 | if (deven & DEVEN_D1F0EN) |
| 142 | start_peg2_link_training(PCI_DEV(0, 1, 0)); |
| 143 | } |
| 144 | |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 145 | static void haswell_setup_misc(void) |
| 146 | { |
| 147 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | |
| 149 | /* Erratum workarounds */ |
| 150 | reg32 = MCHBAR32(0x5f00); |
| 151 | reg32 |= (1 << 9)|(1 << 10); |
| 152 | MCHBAR32(0x5f00) = reg32; |
| 153 | |
| 154 | /* Enable SA Clock Gating */ |
| 155 | reg32 = MCHBAR32(0x5f00); |
| 156 | MCHBAR32(0x5f00) = reg32 | 1; |
| 157 | |
| 158 | /* GPU RC6 workaround for sighting 366252 */ |
| 159 | reg32 = MCHBAR32(0x5d14); |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 160 | reg32 |= (1UL << 31); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 161 | MCHBAR32(0x5d14) = reg32; |
| 162 | |
| 163 | /* VLW */ |
| 164 | reg32 = MCHBAR32(0x6120); |
| 165 | reg32 &= ~(1 << 0); |
| 166 | MCHBAR32(0x6120) = reg32; |
| 167 | |
| 168 | reg32 = MCHBAR32(0x5418); |
| 169 | reg32 |= (1 << 4) | (1 << 5); |
| 170 | MCHBAR32(0x5418) = reg32; |
| 171 | } |
| 172 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 173 | static void haswell_setup_iommu(void) |
| 174 | { |
| 175 | const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); |
| 176 | |
| 177 | if (capid0_a & VTD_DISABLE) |
| 178 | return; |
| 179 | |
| 180 | /* setup BARs: zeroize top 32 bits; set enable bit */ |
| 181 | MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; |
| 182 | MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; |
| 183 | MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; |
| 184 | MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; |
| 185 | |
| 186 | /* set L3HIT2PEND_DIS, lock GFXVTBAR policy cfg registers */ |
| 187 | u32 reg32; |
| 188 | reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); |
| 189 | write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), |
| 190 | reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); |
| 191 | /* clear SPCAPCTRL */ |
| 192 | reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL; |
| 193 | /* set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy cfg registers */ |
| 194 | write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), |
| 195 | reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); |
| 196 | } |
| 197 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 198 | void haswell_early_initialization(int chipset_type) |
| 199 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 200 | /* Setup all BARs required for early PCIe and raminit */ |
| 201 | haswell_setup_bars(); |
| 202 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 203 | /* Setup IOMMU BARs */ |
| 204 | haswell_setup_iommu(); |
| 205 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame^] | 206 | haswell_setup_peg(); |
| 207 | haswell_setup_igd(); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 208 | |
| 209 | haswell_setup_misc(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 210 | } |