Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Elyes HAOUAS | c27014b | 2019-06-23 11:11:53 +0200 | [diff] [blame] | 8 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include "haswell.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 11 | static bool peg_hidden[3]; |
| 12 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | static void haswell_setup_bars(void) |
| 14 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 16 | /* Set up all hardcoded northbridge BARs */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 17 | pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); |
| 18 | pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); |
| 19 | pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); |
| 20 | pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); |
| 21 | pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); |
| 22 | pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | |
| 24 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 25 | pci_write_config8(HOST_BRIDGE, PAM0, 0x30); |
| 26 | pci_write_config8(HOST_BRIDGE, PAM1, 0x33); |
| 27 | pci_write_config8(HOST_BRIDGE, PAM2, 0x33); |
| 28 | pci_write_config8(HOST_BRIDGE, PAM3, 0x33); |
| 29 | pci_write_config8(HOST_BRIDGE, PAM4, 0x33); |
| 30 | pci_write_config8(HOST_BRIDGE, PAM5, 0x33); |
| 31 | pci_write_config8(HOST_BRIDGE, PAM6, 0x33); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | |
| 33 | printk(BIOS_DEBUG, " done.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | } |
| 35 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 36 | static void haswell_setup_igd(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | { |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 38 | bool igd_enabled; |
| 39 | u16 ggc; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 41 | printk(BIOS_DEBUG, "Initializing IGD...\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 43 | igd_enabled = !!(pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 44 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 45 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 46 | ggc &= ~0x3f8; |
| 47 | if (igd_enabled) { |
| 48 | ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1); |
| 49 | ggc &= ~GGC_DISABLE_VGA_IO_DECODE; |
| 50 | } else { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 51 | ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | GGC_DISABLE_VGA_IO_DECODE; |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 52 | } |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 53 | pci_write_config16(HOST_BRIDGE, GGC, ggc); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 54 | |
| 55 | if (!igd_enabled) { |
| 56 | printk(BIOS_DEBUG, "IGD is disabled.\n"); |
| 57 | return; |
| 58 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 59 | |
| 60 | /* Enable 256MB aperture */ |
Angel Pons | 2688607 | 2020-06-07 22:19:21 +0200 | [diff] [blame] | 61 | pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 62 | } |
| 63 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 64 | static void start_peg2_link_training(const pci_devfn_t dev) |
| 65 | { |
| 66 | u32 mask; |
| 67 | |
| 68 | switch (dev) { |
| 69 | case PCI_DEV(0, 1, 2): |
| 70 | mask = DEVEN_D1F2EN; |
| 71 | break; |
| 72 | case PCI_DEV(0, 1, 1): |
| 73 | mask = DEVEN_D1F1EN; |
| 74 | break; |
| 75 | case PCI_DEV(0, 1, 0): |
| 76 | mask = DEVEN_D1F0EN; |
| 77 | break; |
| 78 | default: |
| 79 | printk(BIOS_ERR, "Link training tried on a non-PEG device!\n"); |
| 80 | return; |
| 81 | } |
| 82 | |
| 83 | pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5); |
Chris Morgan | 2806ec9 | 2020-02-05 10:51:46 -0600 | [diff] [blame] | 84 | printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 85 | |
| 86 | /* |
Angel Pons | 84641c8 | 2020-08-29 02:52:09 +0200 | [diff] [blame^] | 87 | * The MRC will perform PCI enumeration, and if it detects a VGA |
| 88 | * device in a PEG slot, it will disable the IGD and not reserve |
| 89 | * any memory for it. Since the memory map is locked by the time |
| 90 | * MRC finishes, the IGD can't be enabled afterwards. Wonderful. |
| 91 | * |
| 92 | * If one really wants to enable the Intel iGPU as primary, hide |
| 93 | * all PEG devices during MRC execution. This will trick the MRC |
| 94 | * into thinking there aren't any, and will enable the IGD. Note |
| 95 | * that PEG AFE settings will not be programmed, which may cause |
| 96 | * stability problems at higher PCIe link speeds. The most ideal |
| 97 | * way to fix this problem for good is to implement native init. |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 98 | */ |
Angel Pons | 84641c8 | 2020-08-29 02:52:09 +0200 | [diff] [blame^] | 99 | if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) { |
| 100 | pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); |
| 101 | peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; |
| 102 | printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", |
| 103 | PCI_FUNC(PCI_DEV2DEVFN(dev))); |
| 104 | } |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | void haswell_unhide_peg(void) |
| 108 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 109 | u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 110 | |
| 111 | for (u8 fn = 0; fn <= 2; fn++) { |
| 112 | if (peg_hidden[fn]) { |
| 113 | deven |= DEVEN_D1F0EN >> fn; |
| 114 | peg_hidden[fn] = false; |
| 115 | printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn); |
| 116 | } |
| 117 | } |
| 118 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 119 | pci_write_config32(HOST_BRIDGE, DEVEN, deven); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | static void haswell_setup_peg(void) |
| 123 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 124 | u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 125 | |
| 126 | if (deven & DEVEN_D1F2EN) |
| 127 | start_peg2_link_training(PCI_DEV(0, 1, 2)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 128 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 129 | if (deven & DEVEN_D1F1EN) |
| 130 | start_peg2_link_training(PCI_DEV(0, 1, 1)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 131 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 132 | if (deven & DEVEN_D1F0EN) |
| 133 | start_peg2_link_training(PCI_DEV(0, 1, 0)); |
| 134 | } |
| 135 | |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 136 | static void haswell_setup_misc(void) |
| 137 | { |
| 138 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 139 | |
| 140 | /* Erratum workarounds */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 141 | reg32 = MCHBAR32(SAPMCTL); |
| 142 | reg32 |= (1 << 9) | (1 << 10); |
| 143 | MCHBAR32(SAPMCTL) = reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | |
| 145 | /* Enable SA Clock Gating */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 146 | reg32 = MCHBAR32(SAPMCTL); |
| 147 | MCHBAR32(SAPMCTL) = reg32 | 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | |
| 149 | /* GPU RC6 workaround for sighting 366252 */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 150 | reg32 = MCHBAR32(SSKPD + 4); |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 151 | reg32 |= (1UL << 31); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 152 | MCHBAR32(SSKPD + 4) = reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 153 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 154 | /* VLW (Virtual Legacy Wire?) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 155 | reg32 = MCHBAR32(0x6120); |
| 156 | reg32 &= ~(1 << 0); |
| 157 | MCHBAR32(0x6120) = reg32; |
| 158 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 159 | reg32 = MCHBAR32(INTRDIRCTL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 160 | reg32 |= (1 << 4) | (1 << 5); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 161 | MCHBAR32(INTRDIRCTL) = reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 162 | } |
| 163 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 164 | static void haswell_setup_iommu(void) |
| 165 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 166 | const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 167 | |
| 168 | if (capid0_a & VTD_DISABLE) |
| 169 | return; |
| 170 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 171 | /* Setup BARs: zeroize top 32 bits; set enable bit */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 172 | MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 173 | MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 174 | MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 175 | MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 176 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 177 | /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 178 | u32 reg32; |
| 179 | reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 180 | write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); |
| 181 | |
| 182 | /* Clear SPCAPCTRL */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 183 | reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 184 | |
| 185 | /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 186 | write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), |
| 187 | reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); |
| 188 | } |
| 189 | |
Angel Pons | e816829 | 2020-07-03 11:42:22 +0200 | [diff] [blame] | 190 | void haswell_early_initialization(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 191 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 192 | /* Setup all BARs required for early PCIe and raminit */ |
| 193 | haswell_setup_bars(); |
| 194 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 195 | /* Setup IOMMU BARs */ |
| 196 | haswell_setup_iommu(); |
| 197 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 198 | haswell_setup_peg(); |
| 199 | haswell_setup_igd(); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 200 | |
| 201 | haswell_setup_misc(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 202 | } |