nb/intel/haswell: Tidy up code and comments
- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 6aad4a3..ea56363 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -28,21 +28,21 @@
{
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
- pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1);
+ pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
+ pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1);
+ pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+ pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
+ pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
printk(BIOS_DEBUG, " done.\n");
}
@@ -55,19 +55,17 @@
printk(BIOS_DEBUG, "Initializing IGD...\n");
- igd_enabled = !!(pci_read_config32(PCI_DEV(0, 0, 0), DEVEN)
- & DEVEN_D2EN);
+ igd_enabled = !!(pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN);
- ggc = pci_read_config16(PCI_DEV(0, 0, 0), GGC);
+ ggc = pci_read_config16(HOST_BRIDGE, GGC);
ggc &= ~0x3f8;
if (igd_enabled) {
ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1);
ggc &= ~GGC_DISABLE_VGA_IO_DECODE;
} else {
- ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) |
- GGC_DISABLE_VGA_IO_DECODE;
+ ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | GGC_DISABLE_VGA_IO_DECODE;
}
- pci_write_config16(PCI_DEV(0, 0, 0), GGC, ggc);
+ pci_write_config16(HOST_BRIDGE, GGC, ggc);
if (!igd_enabled) {
printk(BIOS_DEBUG, "IGD is disabled.\n");
@@ -104,19 +102,18 @@
printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
/*
- * The PEG device is hidden while the MRC runs. This is because the
- * MRC makes configurations that are not ideal if it sees a VGA
- * device in a PEG slot, and it locks registers preventing changes
- * to these configurations.
+ * Hide the PEG device while the MRC runs. This is because the MRC makes
+ * configurations that are not ideal if it sees a VGA device in a PEG slot,
+ * and it locks registers preventing changes to these configurations.
*/
- pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0);
+ pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
}
void haswell_unhide_peg(void)
{
- u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+ u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
for (u8 fn = 0; fn <= 2; fn++) {
if (peg_hidden[fn]) {
@@ -126,17 +123,19 @@
}
}
- pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);
+ pci_write_config32(HOST_BRIDGE, DEVEN, deven);
}
static void haswell_setup_peg(void)
{
- u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+ u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
if (deven & DEVEN_D1F2EN)
start_peg2_link_training(PCI_DEV(0, 1, 2));
+
if (deven & DEVEN_D1F1EN)
start_peg2_link_training(PCI_DEV(0, 1, 1));
+
if (deven & DEVEN_D1F0EN)
start_peg2_link_training(PCI_DEV(0, 1, 0));
}
@@ -146,50 +145,51 @@
u32 reg32;
/* Erratum workarounds */
- reg32 = MCHBAR32(0x5f00);
- reg32 |= (1 << 9)|(1 << 10);
- MCHBAR32(0x5f00) = reg32;
+ reg32 = MCHBAR32(SAPMCTL);
+ reg32 |= (1 << 9) | (1 << 10);
+ MCHBAR32(SAPMCTL) = reg32;
/* Enable SA Clock Gating */
- reg32 = MCHBAR32(0x5f00);
- MCHBAR32(0x5f00) = reg32 | 1;
+ reg32 = MCHBAR32(SAPMCTL);
+ MCHBAR32(SAPMCTL) = reg32 | 1;
/* GPU RC6 workaround for sighting 366252 */
- reg32 = MCHBAR32(0x5d14);
+ reg32 = MCHBAR32(SSKPD + 4);
reg32 |= (1UL << 31);
- MCHBAR32(0x5d14) = reg32;
+ MCHBAR32(SSKPD + 4) = reg32;
- /* VLW */
+ /* VLW (Virtual Legacy Wire?) */
reg32 = MCHBAR32(0x6120);
reg32 &= ~(1 << 0);
MCHBAR32(0x6120) = reg32;
- reg32 = MCHBAR32(0x5418);
+ reg32 = MCHBAR32(INTRDIRCTL);
reg32 |= (1 << 4) | (1 << 5);
- MCHBAR32(0x5418) = reg32;
+ MCHBAR32(INTRDIRCTL) = reg32;
}
static void haswell_setup_iommu(void)
{
- const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
+ const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
if (capid0_a & VTD_DISABLE)
return;
- /* setup BARs: zeroize top 32 bits; set enable bit */
+ /* Setup BARs: zeroize top 32 bits; set enable bit */
MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32;
- MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1;
+ MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1;
MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32;
- MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1;
+ MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1;
- /* set L3HIT2PEND_DIS, lock GFXVTBAR policy cfg registers */
+ /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
u32 reg32;
reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS));
- write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS),
- reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
- /* clear SPCAPCTRL */
+ write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
+
+ /* Clear SPCAPCTRL */
reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL;
- /* set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy cfg registers */
+
+ /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */
write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS),
reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
}