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Arthur Heymans3534c1e2018-12-16 17:17:13 +01001#
2# This file is part of the coreboot project.
3#
4# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
Angel Ponsc69c8dd2018-06-13 14:13:15 +02005# Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
Arthur Heymans3534c1e2018-12-16 17:17:13 +01006#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
9# the Free Software Foundation; either version 2 of the License, or
10# (at your option) any later version.
11#
12# This program is distributed in the hope that it will be useful,
13# but WITHOUT ANY WARRANTY; without even the implied warranty of
14# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15# GNU General Public License for more details.
16#
17
18chip northbridge/intel/x4x # Northbridge
19 device cpu_cluster 0 on # APIC cluster
20 chip cpu/intel/socket_LGA775
21 device lapic 0 on end
22 end
23 chip cpu/intel/model_1067x # CPU
Angel Pons7a61c6c2020-01-01 19:13:53 +010024 device lapic 0xacac off end
Arthur Heymans3534c1e2018-12-16 17:17:13 +010025 end
26 end
27 device domain 0 on # PCI domain
Arthur Heymans3534c1e2018-12-16 17:17:13 +010028 device pci 0.0 on end # Host Bridge
29 device pci 1.0 on end # PEG
30 device pci 2.0 on end # Integrated graphics controller
Angel Pons7a61c6c2020-01-01 19:13:53 +010031 chip southbridge/intel/i82801gx # Southbridge
Arthur Heymans3534c1e2018-12-16 17:17:13 +010032 register "pirqa_routing" = "0x0b"
33 register "pirqb_routing" = "0x0b"
34 register "pirqc_routing" = "0x0b"
35 register "pirqd_routing" = "0x0b"
36 register "pirqe_routing" = "0x80"
37 register "pirqf_routing" = "0x80"
38 register "pirqg_routing" = "0x80"
39 register "pirqh_routing" = "0x0b"
40 # GPI routing
41 # 0 No effect (default)
42 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
43 # 2 SCI (if corresponding GPIO_EN bit is also set)
44
45 register "ide_enable_primary" = "0x1"
Arthur Heymans3534c1e2018-12-16 17:17:13 +010046 register "gpe0_en" = "0x04000440"
47
Arthur Heymansfecf7772019-11-09 14:19:04 +010048 register "gen1_dec" = "0x00000295" # HWM
49
Angel Ponsc69c8dd2018-06-13 14:13:15 +020050 device pci 1b.0 on end # Audio
51 device pci 1c.0 on end # PCIe 1: PCIe x1 slot
Arthur Heymans3534c1e2018-12-16 17:17:13 +010052 device pci 1c.1 on # PCIe 2: NIC
Angel Pons7a61c6c2020-01-01 19:13:53 +010053 device pci 00.0 on end
Arthur Heymans3534c1e2018-12-16 17:17:13 +010054 end
55 device pci 1c.2 off end # PCIe 3
56 device pci 1c.3 off end # PCIe 4
Angel Ponsc69c8dd2018-06-13 14:13:15 +020057 device pci 1d.0 on end # USB
58 device pci 1d.1 on end # USB
59 device pci 1d.2 on end # USB
60 device pci 1d.3 on end # USB
61 device pci 1d.7 on end # USB
62 device pci 1e.0 on end # PCI bridge
Arthur Heymans3534c1e2018-12-16 17:17:13 +010063 device pci 1e.2 off end # AC'97 Audio Controller
64 device pci 1e.3 off end # AC'97 Modem Controller
Angel Ponsc69c8dd2018-06-13 14:13:15 +020065 device pci 1f.0 on end # ISA bridge
66 device pci 1f.1 on end # PATA/IDE
67 device pci 1f.2 on end # SATA
68 device pci 1f.3 on end # SMbus
Arthur Heymans3534c1e2018-12-16 17:17:13 +010069 end
70 end
71end