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Arthur Heymans3534c1e2018-12-16 17:17:13 +01001#
2# This file is part of the coreboot project.
3#
4# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
5#
6# This program is free software; you can redistribute it and/or modify
7# it under the terms of the GNU General Public License as published by
8# the Free Software Foundation; either version 2 of the License, or
9# (at your option) any later version.
10#
11# This program is distributed in the hope that it will be useful,
12# but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14# GNU General Public License for more details.
15#
16
17chip northbridge/intel/x4x # Northbridge
18 device cpu_cluster 0 on # APIC cluster
19 chip cpu/intel/socket_LGA775
20 device lapic 0 on end
21 end
22 chip cpu/intel/model_1067x # CPU
23 device lapic 0xACAC off end
24 end
25 end
26 device domain 0 on # PCI domain
27 subsystemid 0x1043 0x836d inherit
28 device pci 0.0 on end # Host Bridge
29 device pci 1.0 on end # PEG
30 device pci 2.0 on end # Integrated graphics controller
31 chip southbridge/intel/i82801gx # Southbridge
32 register "pirqa_routing" = "0x0b"
33 register "pirqb_routing" = "0x0b"
34 register "pirqc_routing" = "0x0b"
35 register "pirqd_routing" = "0x0b"
36 register "pirqe_routing" = "0x80"
37 register "pirqf_routing" = "0x80"
38 register "pirqg_routing" = "0x80"
39 register "pirqh_routing" = "0x0b"
40 # GPI routing
41 # 0 No effect (default)
42 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
43 # 2 SCI (if corresponding GPIO_EN bit is also set)
44
45 register "ide_enable_primary" = "0x1"
46 register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
47 register "gpe0_en" = "0x04000440"
48
49 device pci 1b.0 on end # Audio
50 device pci 1c.0 on end # PCIe 1
51 device pci 1c.1 on # PCIe 2: NIC
52 device pci 00.0 on
53 end
54 end
55 device pci 1c.2 off end # PCIe 3
56 device pci 1c.3 off end # PCIe 4
57 device pci 1c.4 off end # PCIe 5
58 device pci 1c.5 off end # PCIe 6
59 device pci 1d.0 on end # USB
60 device pci 1d.1 on end # USB
61 device pci 1d.2 on end # USB
62 device pci 1d.3 on end # USB
63 device pci 1d.7 on end # USB
64 device pci 1e.0 on end # PCI bridge
65 device pci 1e.2 off end # AC'97 Audio Controller
66 device pci 1e.3 off end # AC'97 Modem Controller
67 device pci 1f.0 on # ISA bridge
68 chip superio/winbond/w83627dhg
69 device pnp 2e.0 off end # Floppy
70 device pnp 2e.1 on # Parallel port
71 # global
72 irq 0x2c = 0x92
73 # parallel port
74 io 0x60 = 0x378
75 irq 0x70 = 7
76 drq 0x74 = 3
77 end
78 device pnp 2e.2 on # COM1
79 io 0x60 = 0x3f8
80 irq 0x70 = 4
81 end
82 device pnp 2e.3 off end # COM2, IR
83 device pnp 2e.5 on # Keyboard, mouse
84 io 0x60 = 0x60
85 io 0x62 = 0x64
86 irq 0x70 = 1
87 irq 0x72 = 12
88 end
89 device pnp 2e.6 off end # SPI
90 device pnp 2e.7 on end # GPIO6 (all input)
91 device pnp 2e.8 off end # WDT0#, PLED
92 device pnp 2e.9 off end # GPIO2
93 device pnp 2e.109 on # GPIO3
94 irq 0xf0 = 0xf3
95# irq 0xf1 = 0x08
96 end
97 device pnp 2e.209 on # GPIO4
98 irq 0xf4 = 0x00
99 end
100 device pnp 2e.309 off end # GPIO5
101 device pnp 2e.a on # ACPI
102 irq 0x70 = 0
103 irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
104 end
105 device pnp 2e.b on # HWM, front pannel LED
106 io 0x60 = 0x290
107 irq 0x70 = 0
108 end
109 device pnp 2e.c on # PECI, SST
110 irq 0xe0 = 0x10
111 irq 0xe1 = 0x64
112 irq 0xe8 = 0x01
113 end
114 end
115 end
116 device pci 1f.1 on end # PATA/IDE
117 device pci 1f.2 on end # SATA
118 device pci 1f.3 on end # SMbus
119 end
120 end
121end