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Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marshall Dawson9df969a2017-07-25 18:46:46 -06002
Arthur Heymansbab9e2e2021-05-29 07:30:33 +02003#include <acpi/acpi.h>
Kyösti Mälkki021c6212021-01-26 11:28:47 +02004#include <amdblocks/acpi.h>
Arthur Heymansbab9e2e2021-05-29 07:30:33 +02005#include <amdblocks/agesawrapper_call.h>
Elyes Haouasf743e0c2022-10-31 13:46:00 +01006#include <amdblocks/agesawrapper.h>
Michał Żygowski5a662022019-12-02 17:02:00 +01007#include <amdblocks/biosram.h>
Arthur Heymansbab9e2e2021-05-29 07:30:33 +02008#include <amdblocks/psp.h>
Kyösti Mälkkia963acd2019-08-16 20:34:25 +03009#include <arch/romstage.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060010#include <cbmem.h>
Marshall Dawson18b477e2017-09-21 12:27:12 -060011#include <commonlib/helpers.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060012#include <console/console.h>
Arthur Heymansbab9e2e2021-05-29 07:30:33 +020013#include <cpu/amd/mtrr.h>
Elyes Haouasf743e0c2022-10-31 13:46:00 +010014#include <cpu/cpu.h>
Arthur Heymansbab9e2e2021-05-29 07:30:33 +020015#include <cpu/x86/msr.h>
16#include <cpu/x86/mtrr.h>
17#include <cpu/x86/smm.h>
Marshall Dawson3e4e4c52017-11-10 16:08:37 -070018#include <device/device.h>
Arthur Heymansbab9e2e2021-05-29 07:30:33 +020019#include <device/pci_ops.h>
Daniel Kurtzc6c89722018-05-24 17:57:37 -060020#include <elog.h>
Arthur Heymansbab9e2e2021-05-29 07:30:33 +020021#include <program_loading.h>
22#include <romstage_common.h>
23#include <romstage_handoff.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060024#include <soc/northbridge.h>
Felix Helddba32292020-03-31 23:54:44 +020025#include <soc/pci_devs.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -060026#include <soc/southbridge.h>
Arthur Heymans796147f2022-02-15 10:59:41 +010027#include <stdint.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060028
Elyes HAOUASc3385072019-03-21 15:38:06 +010029#include "chip.h"
30
Kyösti Mälkki9e591c42021-01-09 12:37:25 +020031void __weak mainboard_romstage_entry(void)
Martin Roth2c3e3ef2018-04-11 16:35:08 -060032{
33 /* By default, don't do anything */
34}
35
Raul E Rangel873b4e72018-06-12 10:53:55 -060036static void agesa_call(void)
37{
38 post_code(0x37);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +030039 do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
Raul E Rangel873b4e72018-06-12 10:53:55 -060040
41 post_code(0x38);
42 /* APs will not exit amdinitearly */
Kyösti Mälkki6e512c42018-06-14 06:57:05 +030043 do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
Raul E Rangel873b4e72018-06-12 10:53:55 -060044}
45
46static void bsp_agesa_call(void)
47{
48 set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
49 agesa_call();
50}
Arthur Heymansbab9e2e2021-05-29 07:30:33 +020051void __noreturn romstage_main(void)
Marshall Dawson9df969a2017-07-25 18:46:46 -060052{
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060053 msr_t base, mask;
54 msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
55 int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
Kyösti Mälkki9e591c42021-01-09 12:37:25 +020056 int s3_resume = acpi_is_wakeup_s3();
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060057 int i;
58
Felix Helddba32292020-03-31 23:54:44 +020059 soc_enable_psp_early();
Julius Wernercd49cce2019-03-05 16:53:33 -080060 if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
Felix Helddba32292020-03-31 23:54:44 +020061 psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
Raul E Rangel873b4e72018-06-12 10:53:55 -060062
Kyösti Mälkki9e591c42021-01-09 12:37:25 +020063 mainboard_romstage_entry();
Kyösti Mälkki7f50afb2019-09-11 17:12:26 +030064 elog_boot_notify(s3_resume);
Raul E Rangel873b4e72018-06-12 10:53:55 -060065
66 bsp_agesa_call();
67
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060068 if (!s3_resume) {
69 post_code(0x40);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +030070 do_agesawrapper(AMD_INIT_POST, "amdinitpost");
Marshall Dawson9df969a2017-07-25 18:46:46 -060071
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060072 post_code(0x41);
73 /*
74 * TODO: This is a hack to work around current AGESA behavior.
75 * AGESA needs to change to reflect that coreboot owns
76 * the MTRRs.
77 *
78 * After setting up DRAM, AGESA also completes the configuration
79 * of the MTRRs, setting regions to WB. Anything written to
Elyes HAOUASba4dbf82021-01-16 15:02:17 +010080 * memory between now and when CAR is dismantled will be
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060081 * in cache and lost. For now, set the regions UC to ensure
82 * the writes get to DRAM.
83 */
84 for (i = 0 ; i < vmtrrs ; i++) {
85 base = rdmsr(MTRR_PHYS_BASE(i));
86 mask = rdmsr(MTRR_PHYS_MASK(i));
87 if (!(mask.lo & MTRR_PHYS_MASK_VALID))
88 continue;
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060089
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060090 if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
91 base.lo &= ~0x7;
92 base.lo |= MTRR_TYPE_UNCACHEABLE;
93 wrmsr(MTRR_PHYS_BASE(i), base);
94 }
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060095 }
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060096 /* Disable WB from to region 4GB-TOM2. */
97 msr_t sys_cfg = rdmsr(SYSCFG_MSR);
98 sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
99 wrmsr(SYSCFG_MSR, sys_cfg);
100 } else {
101 printk(BIOS_INFO, "S3 detected\n");
102 post_code(0x60);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300103 do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
Marshall Dawson8f2a7e02017-11-01 11:44:48 -0600104
105 post_code(0x61);
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -0600106 }
Marshall Dawson9df969a2017-07-25 18:46:46 -0600107
108 post_code(0x42);
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -0600109 psp_notify_dram();
110
111 post_code(0x43);
Marshall Dawson8f2a7e02017-11-01 11:44:48 -0600112 if (cbmem_recovery(s3_resume))
113 printk(BIOS_CRIT, "Failed to recover cbmem\n");
114 if (romstage_handoff_init(s3_resume))
115 printk(BIOS_ERR, "Failed to set romstage handoff data\n");
Marshall Dawson9df969a2017-07-25 18:46:46 -0600116
Kyösti Mälkki7cdb0472019-08-08 11:16:06 +0300117 if (CONFIG(SMM_TSEG))
118 smm_list_regions();
119
Marshall Dawson18b477e2017-09-21 12:27:12 -0600120 post_code(0x44);
Arthur Heymans876a1b42022-02-15 11:06:10 +0100121 prepare_and_run_postcar();
Arthur Heymans796147f2022-02-15 10:59:41 +0100122}
Marshall Dawson18b477e2017-09-21 12:27:12 -0600123
Arthur Heymans796147f2022-02-15 10:59:41 +0100124void fill_postcar_frame(struct postcar_frame *pcf)
125{
126 uintptr_t top_of_ram = (uintptr_t)cbmem_top();
127 postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
Marshall Dawson9df969a2017-07-25 18:46:46 -0600128
Subrata Banik3eff0372019-09-10 15:51:17 +0530129 /* Cache the TSEG region */
Arthur Heymans796147f2022-02-15 10:59:41 +0100130 postcar_enable_tseg_cache(pcf);
Marshall Dawson9df969a2017-07-25 18:46:46 -0600131}
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700132
133void SetMemParams(AMD_POST_PARAMS *PostParams)
134{
135 const struct soc_amd_stoneyridge_config *cfg;
Kyösti Mälkkie7377552018-06-21 16:20:55 +0300136 const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700137
138 if (!dev || !dev->chip_info) {
Julius Wernere9665952022-01-21 17:06:20 -0800139 printk(BIOS_ERR, "Cannot find SoC devicetree config\n");
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700140 /* In case of a BIOS error, only attempt to set UMA. */
Julius Wernercd49cce2019-03-05 16:53:33 -0800141 PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ?
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700142 UMA_AUTO : UMA_NONE;
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700143 return;
144 }
145
146 cfg = dev->chip_info;
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700147
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700148 PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700149
150 switch (cfg->uma_mode) {
151 case UMAMODE_NONE:
152 PostParams->MemConfig.UmaMode = UMA_NONE;
153 break;
154 case UMAMODE_SPECIFIED_SIZE:
155 PostParams->MemConfig.UmaMode = UMA_SPECIFIED;
156 /* 64 KiB blocks. */
157 PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB);
158 break;
159 case UMAMODE_AUTO_LEGACY:
160 PostParams->MemConfig.UmaMode = UMA_AUTO;
161 PostParams->MemConfig.UmaVersion = UMA_LEGACY;
162 break;
163 case UMAMODE_AUTO_NON_LEGACY:
164 PostParams->MemConfig.UmaMode = UMA_AUTO;
165 PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY;
166 break;
167 }
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700168}
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700169
170void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
171{
172 const struct soc_amd_stoneyridge_config *cfg;
Kyösti Mälkkie7377552018-06-21 16:20:55 +0300173 const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700174 struct _PLATFORM_CONFIGURATION *platform;
175
176 if (!dev || !dev->chip_info) {
Julius Wernere9665952022-01-21 17:06:20 -0800177 printk(BIOS_WARNING, "Cannot find SoC devicetree"
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700178 " config, STAPM unchanged\n");
179 return;
180 }
181 cfg = dev->chip_info;
182 platform = &InitEarly->PlatformConfig;
Richard Spiegelde5d0402018-10-11 08:15:43 -0700183 if ((cfg->stapm_percent) && (cfg->stapm_time_ms) &&
184 (cfg->stapm_power_mw)) {
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700185 platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
186 platform->PlatStapmConfig.CfgStapmTimeConstant =
Richard Spiegelde5d0402018-10-11 08:15:43 -0700187 cfg->stapm_time_ms;
188 platform->PkgPwrLimitDC = cfg->stapm_power_mw;
189 platform->PkgPwrLimitAC = cfg->stapm_power_mw;
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700190 platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
191 }
192}
Kyösti Mälkki021c6212021-01-26 11:28:47 +0200193
194static void migrate_power_state(int is_recovery)
195{
196 struct chipset_power_state *state;
197 state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
198 if (state) {
199 acpi_fill_pm_gpe_state(&state->gpe_state);
200 acpi_pm_gpe_add_events_print_events();
201 }
Kyösti Mälkki021c6212021-01-26 11:28:47 +0200202}
Kyösti Mälkkifa3bc042022-03-31 07:40:10 +0300203CBMEM_CREATION_HOOK(migrate_power_state);