Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 18 | #include <arch/cpu.h> |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame^] | 19 | #include <arch/romstage.h> |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 21 | #include <cpu/x86/msr.h> |
| 22 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | b2a5f0b | 2019-08-04 19:54:32 +0300 | [diff] [blame] | 23 | #include <cpu/x86/smm.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 24 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 25 | #include <cbmem.h> |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 26 | #include <commonlib/helpers.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 27 | #include <console/console.h> |
Marshall Dawson | 3e4e4c5 | 2017-11-10 16:08:37 -0700 | [diff] [blame] | 28 | #include <device/device.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 29 | #include <program_loading.h> |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 30 | #include <romstage_handoff.h> |
Daniel Kurtz | c6c8972 | 2018-05-24 17:57:37 -0600 | [diff] [blame] | 31 | #include <elog.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 32 | #include <amdblocks/agesawrapper.h> |
| 33 | #include <amdblocks/agesawrapper_call.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 34 | #include <soc/northbridge.h> |
Martin Roth | 2c3e3ef | 2018-04-11 16:35:08 -0600 | [diff] [blame] | 35 | #include <soc/romstage.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 36 | #include <soc/southbridge.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 37 | #include <amdblocks/psp.h> |
| 38 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 39 | #include "chip.h" |
| 40 | |
Kyösti Mälkki | c274185 | 2019-08-16 15:13:00 +0300 | [diff] [blame] | 41 | void __weak mainboard_romstage_entry_s3(int s3_resume) |
Martin Roth | 2c3e3ef | 2018-04-11 16:35:08 -0600 | [diff] [blame] | 42 | { |
| 43 | /* By default, don't do anything */ |
| 44 | } |
| 45 | |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 46 | static void load_smu_fw1(void) |
| 47 | { |
| 48 | u32 base, limit, cmd; |
| 49 | |
| 50 | /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ |
| 51 | base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; |
| 52 | limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); |
| 53 | pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); |
| 54 | pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); |
| 55 | |
| 56 | /* Preload a value into "BAR3" and enable it */ |
| 57 | pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); |
| 58 | pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); |
| 59 | |
| 60 | /* Enable memory access and master */ |
| 61 | cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); |
| 62 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; |
| 63 | pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); |
| 64 | |
| 65 | psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); |
| 66 | } |
| 67 | |
| 68 | static void agesa_call(void) |
| 69 | { |
| 70 | post_code(0x37); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 71 | do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 72 | |
| 73 | post_code(0x38); |
| 74 | /* APs will not exit amdinitearly */ |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 75 | do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | static void bsp_agesa_call(void) |
| 79 | { |
| 80 | set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ |
| 81 | agesa_call(); |
| 82 | } |
| 83 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 84 | asmlinkage void car_stage_entry(void) |
| 85 | { |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 86 | struct postcar_frame pcf; |
| 87 | uintptr_t top_of_ram; |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 88 | uintptr_t smm_base; |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 89 | size_t smm_size; |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 90 | msr_t base, mask; |
| 91 | msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 92 | int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 93 | int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 94 | int i; |
| 95 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 96 | console_init(); |
| 97 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 98 | if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 99 | load_smu_fw1(); |
| 100 | |
Kyösti Mälkki | c274185 | 2019-08-16 15:13:00 +0300 | [diff] [blame] | 101 | mainboard_romstage_entry_s3(s3_resume); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 102 | |
| 103 | bsp_agesa_call(); |
| 104 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 105 | if (!s3_resume) { |
| 106 | post_code(0x40); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 107 | do_agesawrapper(AMD_INIT_POST, "amdinitpost"); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 108 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 109 | post_code(0x41); |
| 110 | /* |
| 111 | * TODO: This is a hack to work around current AGESA behavior. |
| 112 | * AGESA needs to change to reflect that coreboot owns |
| 113 | * the MTRRs. |
| 114 | * |
| 115 | * After setting up DRAM, AGESA also completes the configuration |
| 116 | * of the MTRRs, setting regions to WB. Anything written to |
| 117 | * memory between now and and when CAR is dismantled will be |
| 118 | * in cache and lost. For now, set the regions UC to ensure |
| 119 | * the writes get to DRAM. |
| 120 | */ |
| 121 | for (i = 0 ; i < vmtrrs ; i++) { |
| 122 | base = rdmsr(MTRR_PHYS_BASE(i)); |
| 123 | mask = rdmsr(MTRR_PHYS_MASK(i)); |
| 124 | if (!(mask.lo & MTRR_PHYS_MASK_VALID)) |
| 125 | continue; |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 126 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 127 | if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { |
| 128 | base.lo &= ~0x7; |
| 129 | base.lo |= MTRR_TYPE_UNCACHEABLE; |
| 130 | wrmsr(MTRR_PHYS_BASE(i), base); |
| 131 | } |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 132 | } |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 133 | /* Disable WB from to region 4GB-TOM2. */ |
| 134 | msr_t sys_cfg = rdmsr(SYSCFG_MSR); |
| 135 | sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; |
| 136 | wrmsr(SYSCFG_MSR, sys_cfg); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 137 | if (CONFIG(ELOG_BOOT_COUNT)) |
Daniel Kurtz | c6c8972 | 2018-05-24 17:57:37 -0600 | [diff] [blame] | 138 | boot_count_increment(); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 139 | } else { |
| 140 | printk(BIOS_INFO, "S3 detected\n"); |
| 141 | post_code(0x60); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 142 | do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 143 | |
| 144 | post_code(0x61); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 145 | } |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 146 | |
| 147 | post_code(0x42); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 148 | psp_notify_dram(); |
| 149 | |
| 150 | post_code(0x43); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 151 | if (cbmem_recovery(s3_resume)) |
| 152 | printk(BIOS_CRIT, "Failed to recover cbmem\n"); |
| 153 | if (romstage_handoff_init(s3_resume)) |
| 154 | printk(BIOS_ERR, "Failed to set romstage handoff data\n"); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 155 | |
Kyösti Mälkki | 7cdb047 | 2019-08-08 11:16:06 +0300 | [diff] [blame] | 156 | if (CONFIG(SMM_TSEG)) |
| 157 | smm_list_regions(); |
| 158 | |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 159 | post_code(0x44); |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 160 | if (postcar_frame_init(&pcf, 0)) |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 161 | die("Unable to initialize postcar frame.\n"); |
| 162 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 163 | /* |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 164 | * We need to make sure ramstage will be run cached. At this point exact |
| 165 | * location of ramstage in cbmem is not known. Instruct postcar to cache |
| 166 | * 16 megs under cbmem top which is a safe bet to cover ramstage. |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 167 | */ |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 168 | top_of_ram = (uintptr_t) cbmem_top(); |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 169 | postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, |
| 170 | MTRR_TYPE_WRBACK); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 171 | |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 172 | /* Cache the memory-mapped boot media. */ |
Nico Huber | 6ea6775 | 2018-05-27 14:37:52 +0200 | [diff] [blame] | 173 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 174 | |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 175 | /* |
| 176 | * Cache the TSEG region at the top of ram. This region is |
| 177 | * not restricted to SMM mode until SMM has been relocated. |
| 178 | * By setting the region to cacheable it provides faster access |
| 179 | * when relocating the SMM handler as well as using the TSEG |
| 180 | * region for other purposes. |
| 181 | */ |
Kyösti Mälkki | 7db852a | 2019-08-04 20:26:53 +0300 | [diff] [blame] | 182 | smm_region(&smm_base, &smm_size); |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 183 | postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 184 | |
| 185 | post_code(0x45); |
| 186 | run_postcar_phase(&pcf); |
| 187 | |
| 188 | post_code(0x50); /* Should never see this post code. */ |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 189 | } |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 190 | |
| 191 | void SetMemParams(AMD_POST_PARAMS *PostParams) |
| 192 | { |
| 193 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 194 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 195 | |
| 196 | if (!dev || !dev->chip_info) { |
Marshall Dawson | 3e4e4c5 | 2017-11-10 16:08:37 -0700 | [diff] [blame] | 197 | printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 198 | /* In case of a BIOS error, only attempt to set UMA. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 199 | PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 200 | UMA_AUTO : UMA_NONE; |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 201 | return; |
| 202 | } |
| 203 | |
| 204 | cfg = dev->chip_info; |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 205 | |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 206 | PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 207 | |
| 208 | switch (cfg->uma_mode) { |
| 209 | case UMAMODE_NONE: |
| 210 | PostParams->MemConfig.UmaMode = UMA_NONE; |
| 211 | break; |
| 212 | case UMAMODE_SPECIFIED_SIZE: |
| 213 | PostParams->MemConfig.UmaMode = UMA_SPECIFIED; |
| 214 | /* 64 KiB blocks. */ |
| 215 | PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); |
| 216 | break; |
| 217 | case UMAMODE_AUTO_LEGACY: |
| 218 | PostParams->MemConfig.UmaMode = UMA_AUTO; |
| 219 | PostParams->MemConfig.UmaVersion = UMA_LEGACY; |
| 220 | break; |
| 221 | case UMAMODE_AUTO_NON_LEGACY: |
| 222 | PostParams->MemConfig.UmaMode = UMA_AUTO; |
| 223 | PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; |
| 224 | break; |
| 225 | } |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 226 | } |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 227 | |
| 228 | void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) |
| 229 | { |
| 230 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 231 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 232 | struct _PLATFORM_CONFIGURATION *platform; |
| 233 | |
| 234 | if (!dev || !dev->chip_info) { |
| 235 | printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" |
| 236 | " config, STAPM unchanged\n"); |
| 237 | return; |
| 238 | } |
| 239 | cfg = dev->chip_info; |
| 240 | platform = &InitEarly->PlatformConfig; |
Richard Spiegel | de5d040 | 2018-10-11 08:15:43 -0700 | [diff] [blame] | 241 | if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && |
| 242 | (cfg->stapm_power_mw)) { |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 243 | platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; |
| 244 | platform->PlatStapmConfig.CfgStapmTimeConstant = |
Richard Spiegel | de5d040 | 2018-10-11 08:15:43 -0700 | [diff] [blame] | 245 | cfg->stapm_time_ms; |
| 246 | platform->PkgPwrLimitDC = cfg->stapm_power_mw; |
| 247 | platform->PkgPwrLimitAC = cfg->stapm_power_mw; |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 248 | platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; |
| 249 | } |
| 250 | } |