Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 20 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 21 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cpu/cpu.h> |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 24 | #include <cpu/x86/mp.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <fsp/api.h> |
| 28 | #include <fsp/util.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 29 | #include <romstage_handoff.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 30 | #include <soc/iomap.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 31 | #include <soc/cpu.h> |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 32 | #include <soc/flash_ctrlr.h> |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 33 | #include <soc/intel/common/vbt.h> |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 34 | #include <soc/itss.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 35 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 36 | #include <soc/pci_devs.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 37 | #include <spi-generic.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 38 | #include <soc/pm.h> |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 39 | #include <soc/p2sb.h> |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 40 | #include <soc/northbridge.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 41 | |
| 42 | #include "chip.h" |
| 43 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 44 | static void *vbt; |
| 45 | static struct region_device vbt_rdev; |
| 46 | |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 47 | static const char *soc_acpi_name(struct device *dev) |
| 48 | { |
| 49 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 50 | return "PCI0"; |
| 51 | |
| 52 | if (dev->path.type != DEVICE_PATH_PCI) |
| 53 | return NULL; |
| 54 | |
| 55 | switch (dev->path.pci.devfn) { |
| 56 | /* DSDT: acpi/northbridge.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 57 | case SA_DEVFN_ROOT: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 58 | return "MCHC"; |
| 59 | /* DSDT: acpi/lpc.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 60 | case PCH_DEVFN_LPC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 61 | return "LPCB"; |
| 62 | /* DSDT: acpi/xhci.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 63 | case PCH_DEVFN_XHCI: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 64 | return "XHCI"; |
| 65 | /* DSDT: acpi/pch_hda.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 66 | case PCH_DEVFN_HDA: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 67 | return "HDAS"; |
| 68 | /* DSDT: acpi/lpss.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 69 | case PCH_DEVFN_UART0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 70 | return "URT1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 71 | case PCH_DEVFN_UART1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 72 | return "URT2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 73 | case PCH_DEVFN_UART2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 74 | return "URT3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 75 | case PCH_DEVFN_UART3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 76 | return "URT4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 77 | case PCH_DEVFN_SPI0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 78 | return "SPI1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 79 | case PCH_DEVFN_SPI1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 80 | return "SPI2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 81 | case PCH_DEVFN_SPI2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 82 | return "SPI3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 83 | case PCH_DEVFN_PWM: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 84 | return "PWM"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 85 | case PCH_DEVFN_I2C0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 86 | return "I2C0"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 87 | case PCH_DEVFN_I2C1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 88 | return "I2C1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 89 | case PCH_DEVFN_I2C2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 90 | return "I2C2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 91 | case PCH_DEVFN_I2C3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 92 | return "I2C3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 93 | case PCH_DEVFN_I2C4: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 94 | return "I2C4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 95 | case PCH_DEVFN_I2C5: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 96 | return "I2C5"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 97 | case PCH_DEVFN_I2C6: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 98 | return "I2C6"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 99 | case PCH_DEVFN_I2C7: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 100 | return "I2C7"; |
| 101 | /* Storage */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 102 | case PCH_DEVFN_SDCARD: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 103 | return "SDCD"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 104 | case PCH_DEVFN_EMMC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 105 | return "EMMC"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 106 | case PCH_DEVFN_SDIO: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 107 | return "SDIO"; |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 108 | /* PCIe */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 109 | case PCH_DEVFN_PCIE1: |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 110 | return "RP01"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | return NULL; |
| 114 | } |
| 115 | |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 116 | static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 117 | { |
| 118 | if (!vendor || !device) |
| 119 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 120 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 121 | else |
| 122 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 123 | (device << 16) | vendor); |
| 124 | } |
| 125 | |
| 126 | struct pci_operations soc_pci_ops = { |
| 127 | .set_subsystem = &pci_set_subsystem |
| 128 | }; |
| 129 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 130 | static void pci_domain_set_resources(device_t dev) |
| 131 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 132 | assign_resources(dev->link_list); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | static struct device_operations pci_domain_ops = { |
| 136 | .read_resources = pci_domain_read_resources, |
| 137 | .set_resources = pci_domain_set_resources, |
| 138 | .enable_resources = NULL, |
| 139 | .init = NULL, |
| 140 | .scan_bus = pci_domain_scan_bus, |
| 141 | .ops_pci_bus = pci_bus_default_ops, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 142 | .acpi_name = &soc_acpi_name, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 143 | }; |
| 144 | |
| 145 | static struct device_operations cpu_bus_ops = { |
| 146 | .read_resources = DEVICE_NOOP, |
| 147 | .set_resources = DEVICE_NOOP, |
| 148 | .enable_resources = DEVICE_NOOP, |
| 149 | .init = apollolake_init_cpus, |
| 150 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 151 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | static void enable_dev(device_t dev) |
| 155 | { |
| 156 | /* Set the operations if it is a special bus type */ |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 157 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 158 | dev->ops = &pci_domain_ops; |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 159 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 160 | dev->ops = &cpu_bus_ops; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 161 | } |
| 162 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 163 | /* |
| 164 | * If the PCIe root port at function 0 is disabled, |
| 165 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 166 | * The below function will swap the devfn of the first enabled device |
| 167 | * in devicetree and function 0 resides a pci device |
| 168 | * so that it won't confuse coreboot. |
| 169 | */ |
| 170 | static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) |
| 171 | { |
| 172 | device_t func0; |
| 173 | unsigned int devfn; |
| 174 | int i; |
| 175 | unsigned int inc = PCI_DEVFN(0, 1); |
| 176 | |
| 177 | func0 = dev_find_slot(0, devfn0); |
| 178 | if (func0 == NULL) |
| 179 | return; |
| 180 | |
| 181 | /* No more functions if function 0 is disabled. */ |
| 182 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 183 | return; |
| 184 | |
| 185 | devfn = devfn0 + inc; |
| 186 | |
| 187 | /* |
| 188 | * Increase funtion by 1. |
| 189 | * Then find first enabled device to replace func0 |
| 190 | * as that port was move to func0. |
| 191 | */ |
| 192 | for (i = 1; i < num_funcs; i++, devfn += inc) { |
| 193 | device_t dev = dev_find_slot(0, devfn); |
| 194 | if (dev == NULL) |
| 195 | continue; |
| 196 | |
| 197 | if (!dev->enabled) |
| 198 | continue; |
| 199 | /* Found the first enabled device in given dev number */ |
| 200 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 201 | dev->path.pci.devfn = devfn0; |
| 202 | break; |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | static void pcie_override_devicetree_after_silicon_init(void) |
| 207 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 208 | pcie_update_device_tree(PCH_DEVFN_PCIE1, 4); |
| 209 | pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 210 | } |
| 211 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 212 | /* Configure package power limits */ |
| 213 | static void set_power_limits(void) |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 214 | { |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 215 | static struct soc_intel_apollolake_config *cfg; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 216 | struct device *dev = SA_DEV_ROOT; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 217 | msr_t rapl_msr_reg, limit; |
| 218 | uint32_t power_unit; |
| 219 | uint32_t tdp, min_power, max_power; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 220 | uint32_t pl2_val; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 221 | uint32_t *rapl_mmio_reg; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 222 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 223 | if (!dev || !dev->chip_info) { |
| 224 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 225 | return; |
| 226 | } |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 227 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 228 | cfg = dev->chip_info; |
| 229 | |
| 230 | /* Get units */ |
| 231 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 232 | power_unit = 1 << (rapl_msr_reg.lo & 0xf); |
| 233 | |
| 234 | /* Get power defaults for this SKU */ |
| 235 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); |
| 236 | tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 237 | pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 238 | min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; |
| 239 | max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
| 240 | |
| 241 | if (min_power > 0 && tdp < min_power) |
| 242 | tdp = min_power; |
| 243 | |
| 244 | if (max_power > 0 && tdp > max_power) |
| 245 | tdp = max_power; |
| 246 | |
| 247 | /* Set PL1 override value */ |
| 248 | tdp = (cfg->tdp_pl1_override_mw == 0) ? |
| 249 | tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 250 | /* Set PL2 override value */ |
| 251 | pl2_val = (cfg->tdp_pl2_override_mw == 0) ? |
| 252 | pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 253 | |
| 254 | /* Set long term power limit to TDP */ |
| 255 | limit.lo = tdp & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 256 | /* Set PL1 Pkg Power clamp bit */ |
| 257 | limit.lo |= PKG_POWER_LIMIT_CLAMP; |
| 258 | |
| 259 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 260 | limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & |
| 261 | PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; |
| 262 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 263 | /* Set short term power limit PL2 */ |
| 264 | limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; |
| 265 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 266 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 267 | /* Program package power limits in RAPL MSR */ |
| 268 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 269 | printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, |
| 270 | 100 * (tdp % power_unit) / power_unit); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 271 | printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, |
| 272 | 100 * (pl2_val % power_unit) / power_unit); |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 273 | |
| 274 | /* Get the MMIO address */ |
| 275 | rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 276 | |
| 277 | /* Setting RAPL MMIO register for Power limits. |
| 278 | * RAPL driver is using MSR instead of MMIO. |
| 279 | * So, disabled LIMIT_EN bit for MMIO. */ |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 280 | write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 281 | write32(rapl_mmio_reg + 1, limit.hi & ~(PKG_POWER_LIMIT_EN)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 282 | } |
| 283 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 284 | static void soc_init(void *data) |
| 285 | { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 286 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 287 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 288 | /* Save VBT info and mapping */ |
Abhay Kumar | ec2947f | 2016-07-14 18:43:54 -0700 | [diff] [blame] | 289 | vbt = vbt_get(&vbt_rdev); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 290 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 291 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 292 | * default policy that doesn't honor boards' requirements. */ |
| 293 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 294 | |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 295 | fsp_silicon_init(romstage_handoff_is_resume()); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 296 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 297 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 298 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 299 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 300 | /* override 'enabled' setting in device tree if needed */ |
| 301 | pcie_override_devicetree_after_silicon_init(); |
| 302 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 303 | /* |
| 304 | * Keep the P2SB device visible so it and the other devices are |
| 305 | * visible in coreboot for driver support and PCI resource allocation. |
| 306 | * There is a UPD setting for this, but it's more consistent to use |
| 307 | * hide and unhide symmetrically. |
| 308 | */ |
| 309 | p2sb_unhide(); |
| 310 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 311 | /* Allocate ACPI NVS in CBMEM */ |
| 312 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 313 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 314 | /* Set RAPL MSR for Package power limits*/ |
| 315 | set_power_limits(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 316 | } |
| 317 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 318 | static void soc_final(void *data) |
| 319 | { |
| 320 | if (vbt) |
| 321 | rdev_munmap(&vbt_rdev, vbt); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 322 | |
| 323 | /* Disable global reset, just in case */ |
| 324 | global_reset_enable(0); |
| 325 | /* Make sure payload/OS can't trigger global reset */ |
| 326 | global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 327 | } |
| 328 | |
Lee Leahy | bab8be2 | 2017-03-09 09:53:58 -0800 | [diff] [blame] | 329 | static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) |
| 330 | { |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 331 | switch (dev->path.pci.devfn) { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 332 | case PCH_DEVFN_ISH: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 333 | silconfig->IshEnable = 0; |
| 334 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 335 | case PCH_DEVFN_SATA: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 336 | silconfig->EnableSata = 0; |
| 337 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 338 | case PCH_DEVFN_PCIE5: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 339 | silconfig->PcieRootPortEn[0] = 0; |
| 340 | silconfig->PcieRpHotPlug[0] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 341 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 342 | case PCH_DEVFN_PCIE6: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 343 | silconfig->PcieRootPortEn[1] = 0; |
| 344 | silconfig->PcieRpHotPlug[1] = 0; |
| 345 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 346 | case PCH_DEVFN_PCIE1: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 347 | silconfig->PcieRootPortEn[2] = 0; |
| 348 | silconfig->PcieRpHotPlug[2] = 0; |
| 349 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 350 | case PCH_DEVFN_PCIE2: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 351 | silconfig->PcieRootPortEn[3] = 0; |
| 352 | silconfig->PcieRpHotPlug[3] = 0; |
| 353 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 354 | case PCH_DEVFN_PCIE3: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 355 | silconfig->PcieRootPortEn[4] = 0; |
| 356 | silconfig->PcieRpHotPlug[4] = 0; |
| 357 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 358 | case PCH_DEVFN_PCIE4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 359 | silconfig->PcieRootPortEn[5] = 0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 360 | silconfig->PcieRpHotPlug[5] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 361 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 362 | case PCH_DEVFN_XHCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 363 | silconfig->Usb30Mode = 0; |
| 364 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 365 | case PCH_DEVFN_XDCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 366 | silconfig->UsbOtg = 0; |
| 367 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 368 | case PCH_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 369 | silconfig->I2c0Enable = 0; |
| 370 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 371 | case PCH_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 372 | silconfig->I2c1Enable = 0; |
| 373 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 374 | case PCH_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 375 | silconfig->I2c2Enable = 0; |
| 376 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 377 | case PCH_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 378 | silconfig->I2c3Enable = 0; |
| 379 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 380 | case PCH_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 381 | silconfig->I2c4Enable = 0; |
| 382 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 383 | case PCH_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 384 | silconfig->I2c5Enable = 0; |
| 385 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 386 | case PCH_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 387 | silconfig->I2c6Enable = 0; |
| 388 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 389 | case PCH_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 390 | silconfig->I2c7Enable = 0; |
| 391 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 392 | case PCH_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 393 | silconfig->Hsuart0Enable = 0; |
| 394 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 395 | case PCH_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 396 | silconfig->Hsuart1Enable = 0; |
| 397 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 398 | case PCH_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 399 | silconfig->Hsuart2Enable = 0; |
| 400 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 401 | case PCH_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 402 | silconfig->Hsuart3Enable = 0; |
| 403 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 404 | case PCH_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 405 | silconfig->Spi0Enable = 0; |
| 406 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 407 | case PCH_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 408 | silconfig->Spi1Enable = 0; |
| 409 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 410 | case PCH_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 411 | silconfig->Spi2Enable = 0; |
| 412 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 413 | case PCH_DEVFN_SDCARD: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 414 | silconfig->SdcardEnabled = 0; |
| 415 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 416 | case PCH_DEVFN_EMMC: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 417 | silconfig->eMMCEnabled = 0; |
| 418 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 419 | case PCH_DEVFN_SDIO: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 420 | silconfig->SdioEnabled = 0; |
| 421 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 422 | case PCH_DEVFN_SMBUS: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 423 | silconfig->SmbusEnable = 0; |
| 424 | break; |
| 425 | default: |
| 426 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 427 | PCI_SLOT(dev->path.pci.devfn), |
| 428 | PCI_FUNC(dev->path.pci.devfn)); |
| 429 | break; |
| 430 | } |
| 431 | } |
| 432 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 433 | static void parse_devicetree(FSP_S_CONFIG *silconfig) |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 434 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 435 | struct device *dev = SA_DEV_ROOT; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 436 | |
| 437 | if (!dev) { |
| 438 | printk(BIOS_ERR, "Could not find root device\n"); |
| 439 | return; |
| 440 | } |
| 441 | /* Only disable bus 0 devices. */ |
| 442 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 443 | if (!dev->enabled) |
| 444 | disable_dev(dev, silconfig); |
| 445 | } |
| 446 | } |
| 447 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 448 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 449 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 450 | FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 451 | static struct soc_intel_apollolake_config *cfg; |
Kane Chen | 9d490da | 2017-01-11 12:53:58 +0800 | [diff] [blame] | 452 | uint8_t port; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 453 | |
| 454 | /* Load VBT before devicetree-specific config. */ |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 455 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 456 | |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 457 | struct device *dev = SA_DEV_ROOT; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 458 | |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 459 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 460 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 461 | return; |
| 462 | } |
| 463 | |
| 464 | cfg = dev->chip_info; |
| 465 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 466 | /* Parse device tree and disable unused device*/ |
| 467 | parse_devicetree(silconfig); |
| 468 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 469 | silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; |
| 470 | silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; |
| 471 | silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; |
| 472 | silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; |
| 473 | silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; |
| 474 | silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 475 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 476 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 477 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 478 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 479 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 480 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 481 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 482 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 483 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 484 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 485 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 486 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 487 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
| 488 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 489 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 490 | |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 491 | /* Disable monitor mwait since it is broken due to a hardware bug |
| 492 | * without a fix |
| 493 | */ |
Bora Guvendik | 60cc75d | 2016-07-25 14:44:51 -0700 | [diff] [blame] | 494 | silconfig->MonitorMwaitEnable = 0; |
| 495 | |
Venkateswarlu Vinjamuri | 1a5e32c | 2016-10-31 17:15:30 -0700 | [diff] [blame] | 496 | silconfig->SkipMpInit = 1; |
| 497 | |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 498 | /* Disable setting of EISS bit in FSP. */ |
| 499 | silconfig->SpiEiss = 0; |
Ravi Sarawadi | 3a21d0f | 2016-08-10 11:33:56 -0700 | [diff] [blame] | 500 | |
| 501 | /* Disable FSP from locking access to the RTC NVRAM */ |
| 502 | silconfig->RtcLock = 0; |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 503 | |
| 504 | /* Enable Audio clk gate and power gate */ |
| 505 | silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |
| 506 | silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; |
| 507 | /* Bios config lockdown Audio clk and power gate */ |
| 508 | silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; |
| 509 | |
Kane Chen | 9d490da | 2017-01-11 12:53:58 +0800 | [diff] [blame] | 510 | /* USB2 eye diagram settings per port */ |
| 511 | for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { |
| 512 | if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) |
| 513 | silconfig->PortUsb20PerPortTxPeHalf[port] = |
| 514 | cfg->usb2eye[port].Usb20PerPortTxPeHalf; |
| 515 | |
| 516 | if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0) |
| 517 | silconfig->PortUsb20PerPortPeTxiSet[port] = |
| 518 | cfg->usb2eye[port].Usb20PerPortPeTxiSet; |
| 519 | |
| 520 | if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0) |
| 521 | silconfig->PortUsb20PerPortTxiSet[port] = |
| 522 | cfg->usb2eye[port].Usb20PerPortTxiSet; |
| 523 | |
| 524 | if (cfg->usb2eye[port].Usb20HsSkewSel != 0) |
| 525 | silconfig->PortUsb20HsSkewSel[port] = |
| 526 | cfg->usb2eye[port].Usb20HsSkewSel; |
| 527 | |
| 528 | if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0) |
| 529 | silconfig->PortUsb20IUsbTxEmphasisEn[port] = |
| 530 | cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; |
| 531 | |
| 532 | if (cfg->usb2eye[port].Usb20PerPortRXISet != 0) |
| 533 | silconfig->PortUsb20PerPortRXISet[port] = |
| 534 | cfg->usb2eye[port].Usb20PerPortRXISet; |
| 535 | |
| 536 | if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0) |
| 537 | silconfig->PortUsb20HsNpreDrvSel[port] = |
| 538 | cfg->usb2eye[port].Usb20HsNpreDrvSel; |
| 539 | } |
| 540 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 541 | } |
| 542 | |
| 543 | struct chip_operations soc_intel_apollolake_ops = { |
| 544 | CHIP_NAME("Intel Apollolake SOC") |
| 545 | .enable_dev = &enable_dev, |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 546 | .init = &soc_init, |
| 547 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 548 | }; |
| 549 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 550 | static void drop_privilege_all(void) |
| 551 | { |
| 552 | /* Drop privilege level on all the CPUs */ |
| 553 | if (mp_run_on_all_cpus(&enable_untrusted_mode, 1000) < 0) |
| 554 | printk(BIOS_ERR, "failed to enable untrusted mode\n"); |
| 555 | } |
| 556 | |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 557 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 558 | { |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 559 | if (phase == END_OF_FIRMWARE) { |
| 560 | /* Hide the P2SB device to align with previous behavior. */ |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 561 | p2sb_hide(); |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 562 | /* |
| 563 | * As per guidelines BIOS is recommended to drop CPU privilege |
| 564 | * level to IA_UNTRUSTED. After that certain device registers |
| 565 | * and MSRs become inaccessible supposedly increasing system |
| 566 | * security. |
| 567 | */ |
| 568 | drop_privilege_all(); |
| 569 | } |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 570 | } |
| 571 | |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 572 | /* |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 573 | * spi_flash init() needs to run unconditionally on every boot (including |
| 574 | * resume) to allow write protect to be disabled for eventlog and nvram |
| 575 | * updates. This needs to be done as early as possible in ramstage. Thus, add a |
| 576 | * callback for entry into BS_PRE_DEVICE. |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 577 | */ |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 578 | static void spi_flash_init_cb(void *unused) |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 579 | { |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 580 | spi_flash_init(); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 581 | } |
| 582 | |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 583 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); |