Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 1 | #ifndef CPU_X86_MSR_H |
| 2 | #define CPU_X86_MSR_H |
| 3 | |
Stefan Reinauer | 35b6bbb | 2010-03-28 21:26:54 +0000 | [diff] [blame] | 4 | #if defined(__ROMCC__) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 5 | |
| 6 | typedef __builtin_msr_t msr_t; |
| 7 | |
| 8 | static msr_t rdmsr(unsigned long index) |
| 9 | { |
| 10 | return __builtin_rdmsr(index); |
| 11 | } |
| 12 | |
| 13 | static void wrmsr(unsigned long index, msr_t msr) |
| 14 | { |
| 15 | __builtin_wrmsr(index, msr.lo, msr.hi); |
| 16 | } |
| 17 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 18 | #else |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 19 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 20 | typedef struct msr_struct |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 21 | { |
| 22 | unsigned lo; |
| 23 | unsigned hi; |
| 24 | } msr_t; |
| 25 | |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 26 | typedef struct msrinit_struct |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 27 | { |
Elyes HAOUAS | 8ffd050 | 2016-09-01 19:01:41 +0200 | [diff] [blame] | 28 | unsigned index; |
| 29 | msr_t msr; |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 30 | } msrinit_t; |
| 31 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 32 | #if IS_ENABLED(CONFIG_SOC_SETS_MSRS) |
| 33 | msr_t soc_msr_read(unsigned index); |
| 34 | void soc_msr_write(unsigned index, msr_t msr); |
| 35 | |
| 36 | /* Handle MSR references in the other source code */ |
| 37 | static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index) |
| 38 | { |
| 39 | return soc_msr_read(index); |
| 40 | } |
| 41 | |
Elyes HAOUAS | 8ffd050 | 2016-09-01 19:01:41 +0200 | [diff] [blame] | 42 | static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr) |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 43 | { |
| 44 | soc_msr_write(index, msr); |
| 45 | } |
| 46 | #else /* CONFIG_SOC_SETS_MSRS */ |
| 47 | |
Scott Duplichan | 78301d0 | 2010-09-17 21:38:40 +0000 | [diff] [blame] | 48 | /* The following functions require the always_inline due to AMD |
| 49 | * function STOP_CAR_AND_CPU that disables cache as |
Elyes HAOUAS | 918535a | 2016-07-28 21:25:21 +0200 | [diff] [blame] | 50 | * RAM, the cache as RAM stack can no longer be used. Called |
Scott Duplichan | 78301d0 | 2010-09-17 21:38:40 +0000 | [diff] [blame] | 51 | * functions must be inlined to avoid stack usage. Also, the |
| 52 | * compiler must keep local variables register based and not |
| 53 | * allocated them from the stack. With gcc 4.5.0, some functions |
| 54 | * declared as inline are not being inlined. This patch forces |
| 55 | * these functions to always be inlined by adding the qualifier |
| 56 | * __attribute__((always_inline)) to their declaration. |
| 57 | */ |
| 58 | static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 59 | { |
| 60 | msr_t result; |
| 61 | __asm__ __volatile__ ( |
| 62 | "rdmsr" |
| 63 | : "=a" (result.lo), "=d" (result.hi) |
| 64 | : "c" (index) |
| 65 | ); |
| 66 | return result; |
| 67 | } |
| 68 | |
Elyes HAOUAS | 8ffd050 | 2016-09-01 19:01:41 +0200 | [diff] [blame] | 69 | static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 70 | { |
| 71 | __asm__ __volatile__ ( |
| 72 | "wrmsr" |
| 73 | : /* No outputs */ |
| 74 | : "c" (index), "a" (msr.lo), "d" (msr.hi) |
| 75 | ); |
| 76 | } |
| 77 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 78 | #endif /* CONFIG_SOC_SETS_MSRS */ |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 79 | #endif /* __ROMCC__ */ |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 80 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 81 | #endif /* CPU_X86_MSR_H */ |