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Eric Biedermanc84c1902004-10-14 20:13:01 +00001#ifndef CPU_X86_MSR_H
2#define CPU_X86_MSR_H
3
Stefan Reinauer35b6bbb2010-03-28 21:26:54 +00004#if defined(__ROMCC__)
Eric Biedermanc84c1902004-10-14 20:13:01 +00005
6typedef __builtin_msr_t msr_t;
7
8static msr_t rdmsr(unsigned long index)
9{
10 return __builtin_rdmsr(index);
11}
12
13static void wrmsr(unsigned long index, msr_t msr)
14{
15 __builtin_wrmsr(index, msr.lo, msr.hi);
16}
17
arch import user (historical)6ca76362005-07-06 17:17:25 +000018#else
Eric Biedermanc84c1902004-10-14 20:13:01 +000019
Stefan Reinauer14e22772010-04-27 06:56:47 +000020typedef struct msr_struct
Eric Biedermanc84c1902004-10-14 20:13:01 +000021{
22 unsigned lo;
23 unsigned hi;
24} msr_t;
25
Edwin Beasantf333ba02010-06-10 15:24:57 +000026typedef struct msrinit_struct
27{
28 unsigned index;
29 msr_t msr;
30} msrinit_t;
31
Scott Duplichan78301d02010-09-17 21:38:40 +000032/* The following functions require the always_inline due to AMD
33 * function STOP_CAR_AND_CPU that disables cache as
34 * ram, the cache as ram stack can no longer be used. Called
35 * functions must be inlined to avoid stack usage. Also, the
36 * compiler must keep local variables register based and not
37 * allocated them from the stack. With gcc 4.5.0, some functions
38 * declared as inline are not being inlined. This patch forces
39 * these functions to always be inlined by adding the qualifier
40 * __attribute__((always_inline)) to their declaration.
41 */
42static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
Eric Biedermanc84c1902004-10-14 20:13:01 +000043{
44 msr_t result;
45 __asm__ __volatile__ (
46 "rdmsr"
47 : "=a" (result.lo), "=d" (result.hi)
48 : "c" (index)
49 );
50 return result;
51}
52
Scott Duplichan78301d02010-09-17 21:38:40 +000053static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
Eric Biedermanc84c1902004-10-14 20:13:01 +000054{
55 __asm__ __volatile__ (
56 "wrmsr"
57 : /* No outputs */
58 : "c" (index), "a" (msr.lo), "d" (msr.hi)
59 );
60}
61
Myles Watson1d6d45e2009-11-06 17:02:51 +000062#endif /* __ROMCC__ */
Eric Biedermanc84c1902004-10-14 20:13:01 +000063
Eric Biedermanc84c1902004-10-14 20:13:01 +000064#endif /* CPU_X86_MSR_H */