Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 1 | #ifndef CPU_X86_MSR_H |
| 2 | #define CPU_X86_MSR_H |
| 3 | |
Stefan Reinauer | 35b6bbb | 2010-03-28 21:26:54 +0000 | [diff] [blame] | 4 | #if defined(__ROMCC__) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 5 | |
| 6 | typedef __builtin_msr_t msr_t; |
| 7 | |
| 8 | static msr_t rdmsr(unsigned long index) |
| 9 | { |
| 10 | return __builtin_rdmsr(index); |
| 11 | } |
| 12 | |
| 13 | static void wrmsr(unsigned long index, msr_t msr) |
| 14 | { |
| 15 | __builtin_wrmsr(index, msr.lo, msr.hi); |
| 16 | } |
| 17 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 18 | #else |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 19 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 20 | typedef struct msr_struct |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 21 | { |
| 22 | unsigned lo; |
| 23 | unsigned hi; |
| 24 | } msr_t; |
| 25 | |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame^] | 26 | typedef struct msrinit_struct |
| 27 | { |
| 28 | unsigned index; |
| 29 | msr_t msr; |
| 30 | } msrinit_t; |
| 31 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 32 | static inline msr_t rdmsr(unsigned index) |
| 33 | { |
| 34 | msr_t result; |
| 35 | __asm__ __volatile__ ( |
| 36 | "rdmsr" |
| 37 | : "=a" (result.lo), "=d" (result.hi) |
| 38 | : "c" (index) |
| 39 | ); |
| 40 | return result; |
| 41 | } |
| 42 | |
| 43 | static inline void wrmsr(unsigned index, msr_t msr) |
| 44 | { |
| 45 | __asm__ __volatile__ ( |
| 46 | "wrmsr" |
| 47 | : /* No outputs */ |
| 48 | : "c" (index), "a" (msr.lo), "d" (msr.hi) |
| 49 | ); |
| 50 | } |
| 51 | |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 52 | #endif /* __ROMCC__ */ |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 53 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 54 | #endif /* CPU_X86_MSR_H */ |