Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 4 | #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | |
| 6 | /* Chipset types */ |
| 7 | #define HASWELL_MOBILE 0 |
| 8 | #define HASWELL_DESKTOP 1 |
| 9 | #define HASWELL_SERVER 2 |
| 10 | |
Angel Pons | a3cb322 | 2020-09-14 13:15:19 +0200 | [diff] [blame] | 11 | #include "memmap.h" |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 12 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | #include <southbridge/intel/lynxpoint/pch.h> |
| 14 | |
| 15 | /* Everything below this line is ignored in the DSDT */ |
| 16 | #ifndef __ACPI__ |
| 17 | |
| 18 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 19 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | |
Angel Pons | e4156c3 | 2020-09-14 15:47:59 +0200 | [diff] [blame] | 21 | #include "registers/host_bridge.h" |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 22 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | |
| 24 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 25 | |
| 26 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | |
| 28 | /* |
| 29 | * MCHBAR |
| 30 | */ |
| 31 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 32 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 33 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 34 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) |
| 35 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 36 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 37 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 38 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 39 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 40 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 41 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 42 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 43 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 45 | /* As there are many registers, define them on a separate file */ |
Angel Pons | e4156c3 | 2020-09-14 15:47:59 +0200 | [diff] [blame] | 46 | #include "registers/mchbar.h" |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 47 | |
Angel Pons | e220e31 | 2020-07-22 00:55:38 +0200 | [diff] [blame] | 48 | #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ |
| 49 | #define DMAR_LCKDN (1 << 31) |
| 50 | #define SPCAPCTRL (1 << 25) |
| 51 | #define L3HIT2PEND_DIS (1 << 20) |
| 52 | #define PRSCAPDIS (1 << 2) |
| 53 | #define GLBIOTLBINV (1 << 1) |
| 54 | #define GLBCTXTINV (1 << 0) |
| 55 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 56 | /* |
| 57 | * EPBAR - Egress Port Root Complex Register Block |
| 58 | */ |
| 59 | |
Angel Pons | e5ec50c | 2020-09-14 13:22:01 +0200 | [diff] [blame] | 60 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) |
| 61 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) |
| 62 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 63 | |
Angel Pons | 75594e9 | 2020-09-14 14:04:50 +0200 | [diff] [blame^] | 64 | #include "registers/epbar.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | /* |
| 67 | * DMIBAR |
| 68 | */ |
| 69 | |
Angel Pons | e5ec50c | 2020-09-14 13:22:01 +0200 | [diff] [blame] | 70 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) |
| 71 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) |
| 72 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | |
Angel Pons | 75594e9 | 2020-09-14 14:04:50 +0200 | [diff] [blame^] | 74 | #include "registers/dmibar.h" |
Angel Pons | 598ec6a | 2020-07-23 02:37:12 +0200 | [diff] [blame] | 75 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 76 | #ifndef __ASSEMBLER__ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 78 | void intel_northbridge_haswell_finalize_smm(void); |
Kyösti Mälkki | d7205be | 2019-09-27 07:24:17 +0300 | [diff] [blame] | 79 | |
Angel Pons | 73fa035 | 2020-07-03 12:29:03 +0200 | [diff] [blame] | 80 | void mb_late_romstage_setup(void); /* optional */ |
Angel Pons | 2e25ac6 | 2020-07-03 12:06:04 +0200 | [diff] [blame] | 81 | |
Angel Pons | e816829 | 2020-07-03 11:42:22 +0200 | [diff] [blame] | 82 | void haswell_early_initialization(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 83 | void haswell_late_initialization(void); |
Ronald G. Minnich | 4c8465c | 2013-09-30 15:57:21 -0700 | [diff] [blame] | 84 | void set_translation_table(int start, int end, u64 base, int inc); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 85 | void haswell_unhide_peg(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 86 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 87 | void report_platform_info(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 88 | |
Angel Pons | f4fa1e1 | 2020-08-03 14:12:13 +0200 | [diff] [blame] | 89 | int decode_pcie_bar(u32 *const base, u32 *const len); |
| 90 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 91 | #include <device/device.h> |
| 92 | |
| 93 | struct acpi_rsdp; |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 94 | unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 95 | struct acpi_rsdp *rsdp); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 96 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 97 | #endif /* __ASSEMBLER__ */ |
| 98 | #endif /* __ACPI__ */ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 99 | #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ |