Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 18 | #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | |
| 20 | /* Chipset types */ |
| 21 | #define HASWELL_MOBILE 0 |
| 22 | #define HASWELL_DESKTOP 1 |
| 23 | #define HASWELL_SERVER 2 |
| 24 | |
Aaron Durbin | 8ce667e | 2013-02-15 21:45:06 -0600 | [diff] [blame] | 25 | /* Intel Enhanced Debug region */ |
| 26 | #define IED_SIZE CONFIG_IED_REGION_SIZE |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | |
| 28 | /* Northbridge BARs */ |
| 29 | #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ |
| 30 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 31 | #ifndef __ACPI__ |
| 32 | #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ |
| 33 | #else |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 35 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
| 37 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame^] | 38 | #define GFXVT_BASE_ADDRESS 0xfed90000ULL |
| 39 | #define GFXVT_BASE_SIZE 0x1000 |
| 40 | |
| 41 | #define VTVC0_BASE_ADDRESS 0xfed91000ULL |
| 42 | #define VTVC0_BASE_SIZE 0x1000 |
| 43 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | #include <southbridge/intel/lynxpoint/pch.h> |
| 45 | |
| 46 | /* Everything below this line is ignored in the DSDT */ |
| 47 | #ifndef __ACPI__ |
| 48 | |
| 49 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 50 | |
| 51 | #define EPBAR 0x40 |
| 52 | #define MCHBAR 0x48 |
| 53 | #define PCIEXBAR 0x60 |
| 54 | #define DMIBAR 0x68 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | |
| 56 | #define GGC 0x50 /* GMCH Graphics Control */ |
| 57 | |
| 58 | #define DEVEN 0x54 /* Device Enable */ |
Duncan Laurie | 0a7c49e | 2013-06-20 12:40:55 -0700 | [diff] [blame] | 59 | #define DEVEN_D7EN (1 << 14) |
| 60 | #define DEVEN_D4EN (1 << 7) |
| 61 | #define DEVEN_D3EN (1 << 5) |
| 62 | #define DEVEN_D2EN (1 << 4) |
| 63 | #define DEVEN_D1F0EN (1 << 3) |
| 64 | #define DEVEN_D1F1EN (1 << 2) |
| 65 | #define DEVEN_D1F2EN (1 << 1) |
| 66 | #define DEVEN_D0EN (1 << 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 67 | |
| 68 | #define PAM0 0x80 |
| 69 | #define PAM1 0x81 |
| 70 | #define PAM2 0x82 |
| 71 | #define PAM3 0x83 |
| 72 | #define PAM4 0x84 |
| 73 | #define PAM5 0x85 |
| 74 | #define PAM6 0x86 |
| 75 | |
| 76 | #define LAC 0x87 /* Legacy Access Control */ |
| 77 | #define SMRAM 0x88 /* System Management RAM Control */ |
| 78 | #define D_OPEN (1 << 6) |
| 79 | #define D_CLS (1 << 5) |
| 80 | #define D_LCK (1 << 4) |
| 81 | #define G_SMRAME (1 << 3) |
| 82 | #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) |
| 83 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 84 | #define MESEG_BASE 0x70 /* Management Engine Base. */ |
| 85 | #define MESEG_LIMIT 0x78 /* Management Engine Limit. */ |
| 86 | #define REMAPBASE 0x90 /* Remap base. */ |
| 87 | #define REMAPLIMIT 0x98 /* Remap limit. */ |
| 88 | #define TOM 0xa0 /* Top of DRAM in memory controller space. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 89 | #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 90 | #define BDSM 0xb0 /* Base Data Stolen Memory */ |
| 91 | #define BGSM 0xb4 /* Base GTT Stolen Memory */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 92 | #define TSEG 0xb8 /* TSEG base */ |
| 93 | #define TOLUD 0xbc /* Top of Low Used Memory */ |
| 94 | |
| 95 | #define SKPAD 0xdc /* Scratchpad Data */ |
| 96 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame^] | 97 | #define CAPID0_A 0xe4 |
| 98 | #define VTD_DISABLE (1 << 23) |
| 99 | #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ |
| 100 | #define DMAR_LCKDN (1 << 31) |
| 101 | #define SPCAPCTRL (1 << 25) |
| 102 | #define L3HIT2PEND_DIS (1 << 20) |
| 103 | #define PRSCAPDIS (1 << 2) |
| 104 | #define GLBIOTLBINV (1 << 1) |
| 105 | #define GLBCTXTINV (1 << 0) |
| 106 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 108 | |
| 109 | #define BCTRL1 0x3e /* 16bit */ |
| 110 | |
| 111 | |
| 112 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 113 | |
| 114 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * MCHBAR |
| 118 | */ |
| 119 | |
| 120 | #define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) |
| 121 | #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) |
| 122 | #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) |
| 123 | #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) |
| 124 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | #define BIOS_RESET_CPL 0x5da8 /* 8bit */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame^] | 126 | #define GFXVTBAR 0x5400 |
| 127 | #define VTVC0BAR 0x5410 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 128 | |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 129 | /* Some power MSRs are also represented in MCHBAR */ |
| 130 | #define MCH_PKG_POWER_LIMIT_LO 0x59a0 |
| 131 | #define MCH_PKG_POWER_LIMIT_HI 0x59a4 |
| 132 | #define MCH_DDR_POWER_LIMIT_LO 0x58e0 |
| 133 | #define MCH_DDR_POWER_LIMIT_HI 0x58e4 |
| 134 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | /* |
| 136 | * EPBAR - Egress Port Root Complex Register Block |
| 137 | */ |
| 138 | |
| 139 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
| 140 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 141 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 142 | |
| 143 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 144 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 145 | |
| 146 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 147 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 148 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 149 | |
| 150 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 151 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 152 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 153 | |
| 154 | #define EPVC1MTS 0x028 /* 32bit */ |
| 155 | #define EPVC1IST 0x038 /* 64bit */ |
| 156 | |
| 157 | #define EPESD 0x044 /* 32bit */ |
| 158 | |
| 159 | #define EPLE1D 0x050 /* 32bit */ |
| 160 | #define EPLE1A 0x058 /* 64bit */ |
| 161 | #define EPLE2D 0x060 /* 32bit */ |
| 162 | #define EPLE2A 0x068 /* 64bit */ |
| 163 | |
| 164 | #define PORTARB 0x100 /* 256bit */ |
| 165 | |
| 166 | /* |
| 167 | * DMIBAR |
| 168 | */ |
| 169 | |
| 170 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
| 171 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 172 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 173 | |
| 174 | #define DMIVCECH 0x000 /* 32bit */ |
| 175 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 176 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 177 | |
| 178 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 179 | |
| 180 | #define DMIVC0RCAP 0x010 /* 32bit */ |
| 181 | #define DMIVC0RCTL0 0x014 /* 32bit */ |
| 182 | #define DMIVC0RSTS 0x01a /* 16bit */ |
| 183 | |
| 184 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 185 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 186 | #define DMIVC1RSTS 0x026 /* 16bit */ |
| 187 | |
| 188 | #define DMILE1D 0x050 /* 32bit */ |
| 189 | #define DMILE1A 0x058 /* 64bit */ |
| 190 | #define DMILE2D 0x060 /* 32bit */ |
| 191 | #define DMILE2A 0x068 /* 64bit */ |
| 192 | |
| 193 | #define DMILCAP 0x084 /* 32bit */ |
| 194 | #define DMILCTL 0x088 /* 16bit */ |
| 195 | #define DMILSTS 0x08a /* 16bit */ |
| 196 | |
| 197 | #define DMICTL1 0x0f0 /* 32bit */ |
| 198 | #define DMICTL2 0x0fc /* 32bit */ |
| 199 | |
| 200 | #define DMICC 0x208 /* 32bit */ |
| 201 | |
| 202 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 203 | |
| 204 | #ifndef __ASSEMBLER__ |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 205 | #include <compiler.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 206 | static inline void barrier(void) { asm("" ::: "memory"); } |
| 207 | |
| 208 | struct ied_header { |
| 209 | char signature[10]; |
| 210 | u32 size; |
| 211 | u8 reserved[34]; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 212 | } __packed; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 213 | |
Aaron Durbin | 21efd8c | 2013-01-17 09:39:39 -0600 | [diff] [blame] | 214 | #define PCI_DEVICE_ID_HSW_MOBILE 0x0c04 |
| 215 | #define PCI_DEVICE_ID_HSW_ULT 0x0a04 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 216 | |
| 217 | #ifdef __SMM__ |
| 218 | void intel_northbridge_haswell_finalize_smm(void); |
| 219 | #else /* !__SMM__ */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 220 | void haswell_early_initialization(int chipset_type); |
| 221 | void haswell_late_initialization(void); |
Ronald G. Minnich | 4c8465c | 2013-09-30 15:57:21 -0700 | [diff] [blame] | 222 | void set_translation_table(int start, int end, u64 base, int inc); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 223 | |
| 224 | /* debugging functions */ |
| 225 | void print_pci_devices(void); |
| 226 | void dump_pci_device(unsigned dev); |
| 227 | void dump_pci_devices(void); |
| 228 | void dump_spd_registers(void); |
| 229 | void dump_mem(unsigned start, unsigned end); |
| 230 | void report_platform_info(void); |
| 231 | #endif /* !__SMM__ */ |
| 232 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 233 | #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) |
| 234 | #include <device/device.h> |
| 235 | |
| 236 | struct acpi_rsdp; |
| 237 | unsigned long northbridge_write_acpi_tables(device_t device, |
| 238 | unsigned long start, struct acpi_rsdp *rsdp); |
| 239 | #endif |
| 240 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 241 | #endif |
| 242 | #endif |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 243 | #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ |