Angel Pons | 7544e2f | 2020-04-03 01:23:10 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 3 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 4 | #include <bootblock_common.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 5 | #include <stdint.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 6 | #include <arch/io.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 7 | #include <cf9_reset.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 8 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 10 | #include <device/pci_def.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 11 | #include <option.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 12 | #include <northbridge/intel/i945/i945.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 13 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Elyes HAOUAS | ebcd0a8 | 2019-12-13 07:57:37 +0100 | [diff] [blame] | 14 | #include <superio/smsc/lpc47n227/lpc47n227.h> |
| 15 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 16 | /* Override the default lpc decode ranges */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 17 | void mainboard_lpc_decode(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 18 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 19 | int lpt_en = 0; |
Kyösti Mälkki | bee82ab | 2019-12-26 10:57:43 +0200 | [diff] [blame] | 20 | u8 val; |
| 21 | |
| 22 | if (get_option(&val, "lpt") == CB_SUCCESS && val) |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 23 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 24 | |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 25 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 26 | |
| 27 | pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 28 | } |
| 29 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 30 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 31 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 32 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 33 | * but safe anyways" method. |
| 34 | */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 35 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 36 | void bootblock_mainboard_early_init(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 37 | { |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 38 | pnp_devfn_t dev; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 39 | |
Elyes HAOUAS | a5aad2e | 2016-09-19 09:47:16 -0600 | [diff] [blame] | 40 | dev = PNP_DEV(0x2e, 0x00); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 41 | |
Elyes HAOUAS | ebcd0a8 | 2019-12-13 07:57:37 +0100 | [diff] [blame] | 42 | pnp_enter_conf_state(dev); |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 43 | pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ |
| 44 | pnp_write_config(dev, 0x02, 0x88); /* UART power on */ |
| 45 | pnp_write_config(dev, 0x03, 0x72); /* Floppy */ |
| 46 | pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */ |
| 47 | pnp_write_config(dev, 0x14, 0x03); /* Floppy */ |
| 48 | pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ |
| 49 | pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */ |
| 50 | pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ |
| 51 | pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ |
| 52 | pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ |
| 53 | pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ |
| 54 | pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 55 | /* These are the SMI status registers in the SIO: */ |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 56 | pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 57 | |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 58 | pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ |
| 59 | pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ |
| 60 | pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */ |
| 61 | pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */ |
| 62 | pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */ |
| 63 | pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */ |
| 64 | pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */ |
| 65 | pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ |
| 66 | pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 67 | |
Elyes HAOUAS | ebcd0a8 | 2019-12-13 07:57:37 +0100 | [diff] [blame] | 68 | pnp_exit_conf_state(dev); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 69 | } |
| 70 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 71 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 72 | { |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 73 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 74 | RCBA32(D31IP) = 0x00042220; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 75 | |
| 76 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 77 | RCBA16(D31IR) = 0x0232; |
| 78 | RCBA16(D30IR) = 0x3246; |
| 79 | RCBA16(D29IR) = 0x0237; |
| 80 | RCBA16(D28IR) = 0x3201; |
| 81 | RCBA16(D27IR) = 0x3216; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 82 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 83 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 84 | RCBA32(FD) |= FD_INTLAN; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 85 | |
| 86 | /* This should probably go into the ACPI OS Init trap */ |
| 87 | |
| 88 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 89 | RCBA32(0x1e84) = 0x00020001; |
| 90 | RCBA32(0x1e80) = 0x0000fe01; |
| 91 | |
| 92 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 93 | RCBA32(0x1e9c) = 0x000200f0; |
| 94 | RCBA32(0x1e98) = 0x000c0801; |
| 95 | } |
| 96 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 97 | static void init_artec_dongle(void) |
| 98 | { |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 99 | /* Enable 4MB decoding */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 100 | outb(0xf1, 0x88); |
| 101 | outb(0xf4, 0x88); |
| 102 | } |
| 103 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 104 | void mainboard_pre_raminit_config(int s3_resume) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 105 | { |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 106 | init_artec_dongle(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 107 | } |