Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
| 23 | #define __PRE_RAM__ |
| 24 | |
| 25 | /* Configuration of the i945 driver */ |
| 26 | #define CHIPSET_I945GM 1 |
| 27 | #define CHANNEL_XOR_RANDOMIZATION 1 |
| 28 | // Rocky freezing temperature settings: |
| 29 | #define MAXIMUM_SUPPORTED_FREQUENCY 400 |
| 30 | |
| 31 | #include <stdint.h> |
| 32 | #include <string.h> |
| 33 | #include <arch/io.h> |
| 34 | #include <arch/romcc_io.h> |
| 35 | #include <device/pci_def.h> |
| 36 | #include <device/pnp_def.h> |
| 37 | #include <cpu/x86/lapic.h> |
| 38 | |
| 39 | #include "option_table.h" |
| 40 | #include "pc80/mc146818rtc_early.c" |
| 41 | |
| 42 | #include "pc80/serial.c" |
| 43 | #include "arch/i386/lib/console.c" |
| 44 | #include <cpu/x86/bist.h> |
| 45 | |
| 46 | #if CONFIG_USBDEBUG_DIRECT |
| 47 | #define DBGP_DEFAULT 1 |
| 48 | #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" |
| 49 | #include "pc80/usbdebug_direct_serial.c" |
| 50 | #endif |
| 51 | |
| 52 | #include "lib/ramtest.c" |
| 53 | #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" |
| 54 | |
| 55 | #include "northbridge/intel/i945/udelay.c" |
| 56 | |
| 57 | #include "southbridge/intel/i82801gx/i82801gx.h" |
| 58 | static void setup_ich7_gpios(void) |
| 59 | { |
| 60 | printk_debug(" GPIOS..."); |
| 61 | /* General Registers */ |
| 62 | outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 63 | outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 64 | outl(0x7dc07f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 65 | /* Output Control Registers */ |
| 66 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 67 | /* Input Control Registers */ |
| 68 | outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 69 | outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 70 | outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 71 | outl(0x00010030, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ |
| 72 | } |
| 73 | |
| 74 | #include "northbridge/intel/i945/early_init.c" |
| 75 | |
| 76 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 77 | { |
| 78 | return smbus_read_byte(device, address); |
| 79 | } |
| 80 | |
| 81 | #include "northbridge/intel/i945/raminit.h" |
| 82 | #include "northbridge/intel/i945/raminit.c" |
| 83 | #include "northbridge/intel/i945/reset_test.c" |
| 84 | #include "northbridge/intel/i945/errata.c" |
| 85 | #include "northbridge/intel/i945/debug.c" |
| 86 | |
| 87 | static void ich7_enable_lpc(void) |
| 88 | { |
| 89 | // Enable Serial IRQ |
| 90 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 91 | // decode range |
| 92 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); |
| 93 | // decode range |
| 94 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); |
| 95 | // Enable 0x02e0 |
| 96 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); |
| 97 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); |
| 98 | // COM3 decode |
| 99 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); |
| 100 | // COM4 decode |
| 101 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); |
| 102 | } |
| 103 | |
| 104 | |
| 105 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 106 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 107 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 108 | * but safe anyways" method. |
| 109 | */ |
| 110 | static inline void pnp_enter_ext_func_mode(device_t dev) |
| 111 | { |
| 112 | unsigned int port = dev >> 8; |
| 113 | outb(0x55, port); |
| 114 | } |
| 115 | |
| 116 | static void pnp_exit_ext_func_mode(device_t dev) |
| 117 | { |
| 118 | unsigned int port = dev >> 8; |
| 119 | outb(0xaa, port); |
| 120 | } |
| 121 | |
| 122 | static void pnp_write_register(device_t dev, int reg, int val) |
| 123 | { |
| 124 | unsigned int port = dev >> 8; |
| 125 | outb(reg, port); |
| 126 | outb(val, port+1); |
| 127 | } |
| 128 | |
| 129 | static void early_superio_config(void) |
| 130 | { |
| 131 | device_t dev; |
| 132 | |
| 133 | dev=PNP_DEV(0x2e, 0x00); |
| 134 | |
| 135 | pnp_enter_ext_func_mode(dev); |
| 136 | pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes |
| 137 | pnp_write_register(dev, 0x02, 0x88); // UART power on |
| 138 | pnp_write_register(dev, 0x03, 0x72); // Floppy |
| 139 | pnp_write_register(dev, 0x04, 0x01); // EPP + SPP |
| 140 | pnp_write_register(dev, 0x14, 0x03); // Floppy |
| 141 | pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy |
| 142 | pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base |
| 143 | pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base |
| 144 | pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base |
| 145 | pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA |
| 146 | pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA |
| 147 | pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ |
| 148 | /* These are the SMI status registers in the SIO: */ |
| 149 | pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base |
| 150 | |
| 151 | pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR |
| 152 | pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL |
| 153 | pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR |
| 154 | pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL |
| 155 | pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR |
| 156 | pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL |
| 157 | pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR |
| 158 | pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL |
| 159 | pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL |
| 160 | |
| 161 | pnp_exit_ext_func_mode(dev); |
| 162 | } |
| 163 | |
| 164 | static void rcba_config(void) |
| 165 | { |
| 166 | /* Set up virtual channel 0 */ |
| 167 | //RCBA32(0x0014) = 0x80000001; |
| 168 | //RCBA32(0x001c) = 0x03128010; |
| 169 | |
| 170 | /* Device 1f interrupt pin register */ |
| 171 | RCBA32(0x3100) = 0x00042220; |
| 172 | /* Device 1d interrupt pin register */ |
| 173 | RCBA32(0x310c) = 0x00214321; |
| 174 | |
| 175 | /* dev irq route register */ |
| 176 | RCBA16(0x3140) = 0x0232; |
| 177 | RCBA16(0x3142) = 0x3246; |
| 178 | RCBA16(0x3144) = 0x0237; |
| 179 | RCBA16(0x3146) = 0x3201; |
| 180 | RCBA16(0x3148) = 0x3216; |
| 181 | |
| 182 | /* Enable IOAPIC */ |
| 183 | RCBA8(0x31ff) = 0x03; |
| 184 | |
| 185 | /* Enable upper 128bytes of CMOS */ |
| 186 | RCBA32(0x3400) = (1 << 2); |
| 187 | |
| 188 | /* Disable unused devices */ |
| 189 | RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | |
| 190 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; |
| 191 | RCBA32(0x3418) |= (1 << 0); // Required. |
| 192 | |
| 193 | /* Enable PCIe Root Port Clock Gate */ |
| 194 | // RCBA32(0x341c) = 0x00000001; |
| 195 | |
| 196 | /* This should probably go into the ACPI OS Init trap */ |
| 197 | |
| 198 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 199 | RCBA32(0x1e84) = 0x00020001; |
| 200 | RCBA32(0x1e80) = 0x0000fe01; |
| 201 | |
| 202 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 203 | RCBA32(0x1e9c) = 0x000200f0; |
| 204 | RCBA32(0x1e98) = 0x000c0801; |
| 205 | } |
| 206 | |
| 207 | static void early_ich7_init(void) |
| 208 | { |
| 209 | uint8_t reg8; |
| 210 | uint32_t reg32; |
| 211 | |
| 212 | // program secondary mlt XXX byte? |
| 213 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 214 | |
| 215 | // reset rtc power status |
| 216 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 217 | reg8 &= ~(1 << 2); |
| 218 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 219 | |
| 220 | // usb transient disconnect |
| 221 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 222 | reg8 |= (3 << 0); |
| 223 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 224 | |
| 225 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 226 | reg32 |= (1 << 29) | (1 << 17); |
| 227 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 228 | |
| 229 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 230 | reg32 |= (1 << 31) | (1 << 27); |
| 231 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 232 | |
| 233 | RCBA32(0x0088) = 0x0011d000; |
| 234 | RCBA16(0x01fc) = 0x060f; |
| 235 | RCBA32(0x01f4) = 0x86000040; |
| 236 | RCBA32(0x0214) = 0x10030549; |
| 237 | RCBA32(0x0218) = 0x00020504; |
| 238 | RCBA8(0x0220) = 0xc5; |
| 239 | reg32 = RCBA32(0x3410); |
| 240 | reg32 |= (1 << 6); |
| 241 | RCBA32(0x3410) = reg32; |
| 242 | reg32 = RCBA32(0x3430); |
| 243 | reg32 &= ~(3 << 0); |
| 244 | reg32 |= (1 << 0); |
| 245 | RCBA32(0x3430) = reg32; |
| 246 | RCBA32(0x3418) |= (1 << 0); |
| 247 | RCBA16(0x0200) = 0x2008; |
| 248 | RCBA8(0x2027) = 0x0d; |
| 249 | RCBA16(0x3e08) |= (1 << 7); |
| 250 | RCBA16(0x3e48) |= (1 << 7); |
| 251 | RCBA32(0x3e0e) |= (1 << 7); |
| 252 | RCBA32(0x3e4e) |= (1 << 7); |
| 253 | |
| 254 | // next step only on ich7m b0 and later: |
| 255 | reg32 = RCBA32(0x2034); |
| 256 | reg32 &= ~(0x0f << 16); |
| 257 | reg32 |= (5 << 16); |
| 258 | RCBA32(0x2034) = reg32; |
| 259 | } |
| 260 | |
| 261 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
| 262 | #include "southbridge/intel/i82801gx/cmos_failover.c" |
| 263 | #endif |
| 264 | |
| 265 | static void init_artec_dongle(void) |
| 266 | { |
| 267 | // Enable 4MB decoding |
| 268 | outb(0xf1, 0x88); |
| 269 | outb(0xf4, 0x88); |
| 270 | } |
| 271 | |
| 272 | #include <cbmem.h> |
| 273 | |
| 274 | // Now, this needs to be included because it relies on the symbol |
| 275 | // __PRE_RAM__ being set during CAR stage (in order to compile the |
| 276 | // BSS free versions of the functions). Either rewrite the code |
| 277 | // to be always BSS free, or invent a flag that's better suited than |
| 278 | // __PRE_RAM__ to determine whether we're in ram init stage (stage 1) |
| 279 | // |
| 280 | #include "lib/cbmem.c" |
| 281 | |
| 282 | void real_main(unsigned long bist) |
| 283 | { |
| 284 | u32 reg32; |
| 285 | int boot_mode = 0; |
| 286 | |
| 287 | if (bist == 0) { |
| 288 | enable_lapic(); |
| 289 | } |
| 290 | |
| 291 | ich7_enable_lpc(); |
| 292 | early_superio_config(); |
| 293 | |
| 294 | /* Set up the console */ |
| 295 | uart_init(); |
| 296 | |
| 297 | #if CONFIG_USBDEBUG_DIRECT |
| 298 | i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); |
| 299 | early_usbdebug_direct_init(); |
| 300 | #endif |
| 301 | |
| 302 | console_init(); |
| 303 | |
| 304 | /* Halt if there was a built in self test failure */ |
| 305 | report_bist_failure(bist); |
| 306 | |
| 307 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 308 | printk_debug("soft reset detected.\n"); |
| 309 | boot_mode = 1; |
| 310 | } |
| 311 | |
| 312 | /* Perform some early chipset initialization required |
| 313 | * before RAM initialization can work |
| 314 | */ |
| 315 | i945_early_initialization(); |
| 316 | |
| 317 | /* This has to happen after i945_early_initialization() */ |
| 318 | init_artec_dongle(); |
| 319 | |
| 320 | /* Read PM1_CNT */ |
| 321 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
| 322 | printk_debug("PM1_CNT: %08x\n", reg32); |
| 323 | if (((reg32 >> 10) & 7) == 5) { |
| 324 | #if CONFIG_HAVE_ACPI_RESUME |
| 325 | printk_debug("Resume from S3 detected.\n"); |
| 326 | boot_mode = 2; |
| 327 | /* Clear SLP_TYPE. This will break stage2 but |
| 328 | * we care for that when we get there. |
| 329 | */ |
| 330 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
| 331 | |
| 332 | #else |
| 333 | printk_debug("Resume from S3 detected, but disabled.\n"); |
| 334 | #endif |
| 335 | } |
| 336 | |
| 337 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 338 | enable_smbus(); |
| 339 | |
| 340 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 341 | dump_spd_registers(); |
| 342 | #endif |
| 343 | |
| 344 | sdram_initialize(boot_mode); |
| 345 | |
| 346 | /* Perform some initialization that must run before stage2 */ |
| 347 | early_ich7_init(); |
| 348 | |
| 349 | /* This should probably go away. Until now it is required |
| 350 | * and mainboard specific |
| 351 | */ |
| 352 | rcba_config(); |
| 353 | |
| 354 | /* Chipset Errata! */ |
| 355 | fixup_i945_errata(); |
| 356 | |
| 357 | /* Initialize the internal PCIe links before we go into stage2 */ |
| 358 | i945_late_initialization(); |
| 359 | |
| 360 | #if !CONFIG_HAVE_ACPI_RESUME |
| 361 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 362 | #if defined(DEBUG_RAM_SETUP) |
| 363 | sdram_dump_mchbar_registers(); |
| 364 | |
| 365 | { |
| 366 | /* This will not work if TSEG is in place! */ |
| 367 | u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); |
| 368 | |
| 369 | printk_debug("TOM: 0x%08x\n", tom); |
| 370 | ram_check(0x00000000, 0x000a0000); |
| 371 | ram_check(0x00100000, tom); |
| 372 | } |
| 373 | #endif |
| 374 | #endif |
| 375 | #endif |
| 376 | |
| 377 | MCHBAR16(SSKPD) = 0xCAFE; |
| 378 | |
| 379 | #if CONFIG_HAVE_ACPI_RESUME |
| 380 | /* Start address of high memory tables */ |
| 381 | unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; |
| 382 | |
| 383 | /* If there is no high memory area, we didn't boot before, so |
| 384 | * this is not a resume. In that case we just create the cbmem toc. |
| 385 | */ |
| 386 | if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { |
| 387 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 388 | |
| 389 | /* copy 1MB - 64K to high tables ram_base to prevent memory corruption |
| 390 | * through stage 2. We could keep stuff like stack and heap in high tables |
| 391 | * memory completely, but that's a wonderful clean up task for another |
| 392 | * day. |
| 393 | */ |
| 394 | if (resume_backup_memory) |
| 395 | memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); |
| 396 | |
| 397 | /* Magic for S3 resume */ |
| 398 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 399 | } |
| 400 | #endif |
| 401 | } |
| 402 | |
| 403 | #include "cpu/intel/model_6ex/cache_as_ram_disable.c" |