Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 17 | #include <stdint.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 18 | #include <arch/io.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 19 | #include <cf9_reset.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 20 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 22 | #include <device/pci_def.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 23 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 24 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 8a7d34b | 2010-02-22 09:15:13 +0000 | [diff] [blame] | 25 | #include <console/console.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 26 | #include <arch/romstage.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 27 | #include <northbridge/intel/i945/i945.h> |
| 28 | #include <northbridge/intel/i945/raminit.h> |
| 29 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 30 | #include <southbridge/intel/common/pmclib.h> |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 31 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 32 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 33 | /* Override the default lpc decode ranges */ |
| 34 | static void mb_lpc_decode(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 35 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 36 | int lpt_en = 0; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 37 | if (read_option(lpt, 0) != 0) |
| 38 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 39 | |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 40 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 41 | |
| 42 | pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 43 | } |
| 44 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 45 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 46 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 47 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 48 | * but safe anyways" method. |
| 49 | */ |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 50 | static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 51 | { |
| 52 | unsigned int port = dev >> 8; |
| 53 | outb(0x55, port); |
| 54 | } |
| 55 | |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 56 | static void pnp_exit_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 57 | { |
| 58 | unsigned int port = dev >> 8; |
| 59 | outb(0xaa, port); |
| 60 | } |
| 61 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 62 | static void early_superio_config(void) |
| 63 | { |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 64 | pnp_devfn_t dev; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 65 | |
Elyes HAOUAS | a5aad2e | 2016-09-19 09:47:16 -0600 | [diff] [blame] | 66 | dev = PNP_DEV(0x2e, 0x00); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 67 | |
| 68 | pnp_enter_ext_func_mode(dev); |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 69 | pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ |
| 70 | pnp_write_config(dev, 0x02, 0x88); /* UART power on */ |
| 71 | pnp_write_config(dev, 0x03, 0x72); /* Floppy */ |
| 72 | pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */ |
| 73 | pnp_write_config(dev, 0x14, 0x03); /* Floppy */ |
| 74 | pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ |
| 75 | pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */ |
| 76 | pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ |
| 77 | pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ |
| 78 | pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ |
| 79 | pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ |
| 80 | pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 81 | /* These are the SMI status registers in the SIO: */ |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 82 | pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 83 | |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 84 | pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ |
| 85 | pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ |
| 86 | pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */ |
| 87 | pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */ |
| 88 | pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */ |
| 89 | pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */ |
| 90 | pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */ |
| 91 | pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ |
| 92 | pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 93 | |
| 94 | pnp_exit_ext_func_mode(dev); |
| 95 | } |
| 96 | |
| 97 | static void rcba_config(void) |
| 98 | { |
| 99 | /* Set up virtual channel 0 */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 100 | |
| 101 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 102 | RCBA32(D31IP) = 0x00042220; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 103 | |
| 104 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 105 | RCBA16(D31IR) = 0x0232; |
| 106 | RCBA16(D30IR) = 0x3246; |
| 107 | RCBA16(D29IR) = 0x0237; |
| 108 | RCBA16(D28IR) = 0x3201; |
| 109 | RCBA16(D27IR) = 0x3216; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 110 | |
| 111 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 112 | RCBA8(OIC) = 0x03; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 113 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 114 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 115 | RCBA32(FD) |= FD_INTLAN; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 116 | |
| 117 | /* This should probably go into the ACPI OS Init trap */ |
| 118 | |
| 119 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 120 | RCBA32(0x1e84) = 0x00020001; |
| 121 | RCBA32(0x1e80) = 0x0000fe01; |
| 122 | |
| 123 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 124 | RCBA32(0x1e9c) = 0x000200f0; |
| 125 | RCBA32(0x1e98) = 0x000c0801; |
| 126 | } |
| 127 | |
| 128 | static void early_ich7_init(void) |
| 129 | { |
| 130 | uint8_t reg8; |
| 131 | uint32_t reg32; |
| 132 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 133 | /* program secondary mlt XXX byte? */ |
Elyes HAOUAS | 6df210b | 2019-10-25 14:05:17 +0200 | [diff] [blame] | 134 | pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 135 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 136 | /* reset rtc power status */ |
Elyes HAOUAS | 6df210b | 2019-10-25 14:05:17 +0200 | [diff] [blame] | 137 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
| 138 | reg8 &= ~RTC_BATTERY_DEAD; |
| 139 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 140 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 141 | /* usb transient disconnect */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 142 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 143 | reg8 |= (3 << 0); |
| 144 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 145 | |
| 146 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 147 | reg32 |= (1 << 29) | (1 << 17); |
| 148 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 149 | |
| 150 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 151 | reg32 |= (1 << 31) | (1 << 27); |
| 152 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 153 | |
Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 154 | ich7_setup_cir(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 155 | } |
| 156 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 157 | static void init_artec_dongle(void) |
| 158 | { |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 159 | /* Enable 4MB decoding */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 160 | outb(0xf1, 0x88); |
| 161 | outb(0xf4, 0x88); |
| 162 | } |
| 163 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 164 | void mainboard_romstage_entry(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 165 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 166 | int s3resume = 0; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 167 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 168 | enable_lapic(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 169 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 170 | i82801gx_lpc_setup(); |
| 171 | mb_lpc_decode(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 172 | early_superio_config(); |
| 173 | |
| 174 | /* Set up the console */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 175 | console_init(); |
| 176 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 177 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 178 | system_reset(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /* Perform some early chipset initialization required |
| 182 | * before RAM initialization can work |
| 183 | */ |
| 184 | i945_early_initialization(); |
| 185 | |
| 186 | /* This has to happen after i945_early_initialization() */ |
| 187 | init_artec_dongle(); |
| 188 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 189 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 190 | |
| 191 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 192 | enable_smbus(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 193 | |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 194 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 195 | dump_spd_registers(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 196 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 197 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 198 | |
| 199 | /* Perform some initialization that must run before stage2 */ |
| 200 | early_ich7_init(); |
| 201 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 202 | /* This should probably go away. Until now it is required |
| 203 | * and mainboard specific |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 204 | */ |
| 205 | rcba_config(); |
| 206 | |
| 207 | /* Chipset Errata! */ |
| 208 | fixup_i945_errata(); |
| 209 | |
| 210 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 211 | i945_late_initialization(s3resume); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 212 | } |