Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 17 | #include <bootblock_common.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 19 | #include <arch/io.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 20 | #include <cf9_reset.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 21 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 23 | #include <device/pci_def.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 24 | #include <pc80/mc146818rtc.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 25 | #include <northbridge/intel/i945/i945.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 26 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 27 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 28 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 29 | /* Override the default lpc decode ranges */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 30 | void mainboard_lpc_decode(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 31 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 32 | int lpt_en = 0; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 33 | if (read_option(lpt, 0) != 0) |
| 34 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 35 | |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 36 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 37 | |
| 38 | pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 39 | } |
| 40 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 41 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 42 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 43 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 44 | * but safe anyways" method. |
| 45 | */ |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 46 | static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 47 | { |
| 48 | unsigned int port = dev >> 8; |
| 49 | outb(0x55, port); |
| 50 | } |
| 51 | |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 52 | static void pnp_exit_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 53 | { |
| 54 | unsigned int port = dev >> 8; |
| 55 | outb(0xaa, port); |
| 56 | } |
| 57 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 58 | void bootblock_mainboard_early_init(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 59 | { |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 60 | pnp_devfn_t dev; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 61 | |
Elyes HAOUAS | a5aad2e | 2016-09-19 09:47:16 -0600 | [diff] [blame] | 62 | dev = PNP_DEV(0x2e, 0x00); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 63 | |
| 64 | pnp_enter_ext_func_mode(dev); |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 65 | pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ |
| 66 | pnp_write_config(dev, 0x02, 0x88); /* UART power on */ |
| 67 | pnp_write_config(dev, 0x03, 0x72); /* Floppy */ |
| 68 | pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */ |
| 69 | pnp_write_config(dev, 0x14, 0x03); /* Floppy */ |
| 70 | pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ |
| 71 | pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */ |
| 72 | pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ |
| 73 | pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ |
| 74 | pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ |
| 75 | pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ |
| 76 | pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 77 | /* These are the SMI status registers in the SIO: */ |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 78 | pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 79 | |
Elyes HAOUAS | cd7adbf | 2019-10-11 14:03:52 +0200 | [diff] [blame] | 80 | pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ |
| 81 | pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ |
| 82 | pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */ |
| 83 | pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */ |
| 84 | pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */ |
| 85 | pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */ |
| 86 | pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */ |
| 87 | pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ |
| 88 | pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 89 | |
| 90 | pnp_exit_ext_func_mode(dev); |
| 91 | } |
| 92 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 93 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 94 | { |
| 95 | /* Set up virtual channel 0 */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 96 | |
| 97 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 98 | RCBA32(D31IP) = 0x00042220; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 99 | |
| 100 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 101 | RCBA16(D31IR) = 0x0232; |
| 102 | RCBA16(D30IR) = 0x3246; |
| 103 | RCBA16(D29IR) = 0x0237; |
| 104 | RCBA16(D28IR) = 0x3201; |
| 105 | RCBA16(D27IR) = 0x3216; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 106 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 107 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 108 | RCBA32(FD) |= FD_INTLAN; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 109 | |
| 110 | /* This should probably go into the ACPI OS Init trap */ |
| 111 | |
| 112 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 113 | RCBA32(0x1e84) = 0x00020001; |
| 114 | RCBA32(0x1e80) = 0x0000fe01; |
| 115 | |
| 116 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 117 | RCBA32(0x1e9c) = 0x000200f0; |
| 118 | RCBA32(0x1e98) = 0x000c0801; |
| 119 | } |
| 120 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 121 | static void init_artec_dongle(void) |
| 122 | { |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 123 | /* Enable 4MB decoding */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 124 | outb(0xf1, 0x88); |
| 125 | outb(0xf4, 0x88); |
| 126 | } |
| 127 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 128 | void mainboard_pre_raminit_config(int s3_resume) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 129 | { |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 130 | init_artec_dongle(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 131 | } |