Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 1 | #include <console/console.h> |
| 2 | #include <arch/io.h> |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame^] | 3 | #include <arch/ioapic.h> |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 4 | #include <stdint.h> |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 7 | #include <stdlib.h> |
| 8 | #include <string.h> |
| 9 | #include <bitops.h> |
| 10 | #include "chip.h" |
Myles Watson | 2e67273 | 2009-11-12 16:38:03 +0000 | [diff] [blame] | 11 | #include <delay.h> |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 12 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 13 | #if CONFIG_WRITE_HIGH_TABLES==1 |
Myles Watson | 0520d55 | 2009-05-11 22:44:14 +0000 | [diff] [blame] | 14 | #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB |
| 15 | extern uint64_t high_tables_base, high_tables_size; |
| 16 | #endif |
| 17 | |
Valdimir Serbinenko | 7339f36 | 2010-05-03 16:21:52 +0000 | [diff] [blame] | 18 | #define CMOS_ADDR_PORT 0x70 |
| 19 | #define CMOS_DATA_PORT 0x71 |
| 20 | #define HIGH_RAM_ADDR 0x35 |
| 21 | #define LOW_RAM_ADDR 0x34 |
| 22 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 23 | static void cpu_pci_domain_set_resources(device_t dev) |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 24 | { |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 25 | u32 pci_tolm = find_pci_tolm(dev->link_list); |
Valdimir Serbinenko | 7339f36 | 2010-05-03 16:21:52 +0000 | [diff] [blame] | 26 | unsigned long tomk = 0, tolmk; |
| 27 | int idx; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 28 | |
Valdimir Serbinenko | 7339f36 | 2010-05-03 16:21:52 +0000 | [diff] [blame] | 29 | outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT); |
| 30 | tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; |
| 31 | outb (LOW_RAM_ADDR, CMOS_ADDR_PORT); |
| 32 | tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; |
| 33 | tomk += 16 * 1024; |
Ronald G. Minnich | 9cf642b | 2006-09-13 04:12:35 +0000 | [diff] [blame] | 34 | |
Valdimir Serbinenko | 7339f36 | 2010-05-03 16:21:52 +0000 | [diff] [blame] | 35 | printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", |
| 36 | tomk, tomk / 1024); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 37 | |
Valdimir Serbinenko | 7339f36 | 2010-05-03 16:21:52 +0000 | [diff] [blame] | 38 | /* Compute the top of Low memory */ |
| 39 | tolmk = pci_tolm >> 10; |
| 40 | if (tolmk >= tomk) { |
| 41 | /* The PCI hole does not overlap the memory. */ |
| 42 | tolmk = tomk; |
| 43 | } |
| 44 | |
| 45 | /* Report the memory regions. */ |
| 46 | idx = 10; |
| 47 | ram_resource(dev, idx++, 0, 640); |
| 48 | ram_resource(dev, idx++, 768, tolmk - 768); |
Myles Watson | 0520d55 | 2009-05-11 22:44:14 +0000 | [diff] [blame] | 49 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 50 | #if CONFIG_WRITE_HIGH_TABLES==1 |
Valdimir Serbinenko | 7339f36 | 2010-05-03 16:21:52 +0000 | [diff] [blame] | 51 | /* Leave some space for ACPI, PIRQ and MP tables */ |
| 52 | high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; |
| 53 | high_tables_size = HIGH_TABLES_SIZE * 1024; |
Myles Watson | 0520d55 | 2009-05-11 22:44:14 +0000 | [diff] [blame] | 54 | #endif |
Valdimir Serbinenko | 7339f36 | 2010-05-03 16:21:52 +0000 | [diff] [blame] | 55 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 56 | assign_resources(dev->link_list); |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 57 | } |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 58 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 59 | static void cpu_pci_domain_read_resources(struct device *dev) |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 60 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 61 | struct resource *res; |
| 62 | |
| 63 | pci_domain_read_resources(dev); |
| 64 | |
| 65 | /* Reserve space for the IOAPIC. This should be in the Southbridge, |
| 66 | * but I couldn't tell which device to put it in. */ |
| 67 | res = new_resource(dev, 2); |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame^] | 68 | res->base = IO_APIC_ADDR; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 69 | res->size = 0x100000UL; |
| 70 | res->limit = 0xffffffffUL; |
| 71 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 72 | IORESOURCE_ASSIGNED; |
| 73 | |
| 74 | /* Reserve space for the LAPIC. There's one in every processor, but |
| 75 | * the space only needs to be reserved once, so we do it here. */ |
| 76 | res = new_resource(dev, 3); |
| 77 | res->base = 0xfee00000UL; |
| 78 | res->size = 0x10000UL; |
| 79 | res->limit = 0xffffffffUL; |
| 80 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 81 | IORESOURCE_ASSIGNED; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | static struct device_operations pci_domain_ops = { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 85 | .read_resources = cpu_pci_domain_read_resources, |
| 86 | .set_resources = cpu_pci_domain_set_resources, |
Myles Watson | 7eac445 | 2010-06-17 16:16:56 +0000 | [diff] [blame] | 87 | .enable_resources = NULL, |
| 88 | .init = NULL, |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 89 | .scan_bus = pci_domain_scan_bus, |
| 90 | }; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 91 | |
| 92 | static void enable_dev(struct device *dev) |
| 93 | { |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 94 | /* Set the operations if it is a special bus type */ |
| 95 | if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { |
| 96 | dev->ops = &pci_domain_ops; |
Eric Biederman | a9e632c | 2004-11-18 22:38:08 +0000 | [diff] [blame] | 97 | pci_set_method(dev); |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 98 | } |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 99 | } |
| 100 | |
Patrick Georgi | 35784b6 | 2010-04-08 12:47:35 +0000 | [diff] [blame] | 101 | struct chip_operations mainboard_emulation_qemu_x86_ops = { |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 102 | CHIP_NAME("QEMU Northbridge") |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 103 | .enable_dev = enable_dev, |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 104 | }; |