Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 1 | #include <console/console.h> |
| 2 | #include <arch/io.h> |
| 3 | #include <stdint.h> |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 6 | #include <stdlib.h> |
| 7 | #include <string.h> |
| 8 | #include <bitops.h> |
| 9 | #include "chip.h" |
| 10 | #include "northbridge.h" |
| 11 | |
Stefan Reinauer | e4932dc | 2004-11-02 20:33:12 +0000 | [diff] [blame] | 12 | static void ram_resource(device_t dev, unsigned long index, |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 13 | unsigned long basek, unsigned long sizek) |
Stefan Reinauer | e4932dc | 2004-11-02 20:33:12 +0000 | [diff] [blame] | 14 | { |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 15 | struct resource *resource; |
Stefan Reinauer | e4932dc | 2004-11-02 20:33:12 +0000 | [diff] [blame] | 16 | |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 17 | if (!sizek) { |
| 18 | return; |
| 19 | } |
| 20 | resource = new_resource(dev, index); |
| 21 | resource->base = ((resource_t)basek) << 10; |
| 22 | resource->size = ((resource_t)sizek) << 10; |
| 23 | resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ |
| 24 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
Stefan Reinauer | e4932dc | 2004-11-02 20:33:12 +0000 | [diff] [blame] | 25 | } |
| 26 | |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 27 | static void tolm_test(void *gp, struct device *dev, struct resource *new) |
| 28 | { |
| 29 | struct resource **best_p = gp; |
| 30 | struct resource *best; |
| 31 | best = *best_p; |
| 32 | if (!best || (best->base > new->base)) { |
| 33 | best = new; |
| 34 | } |
| 35 | *best_p = best; |
| 36 | } |
| 37 | |
| 38 | static uint32_t find_pci_tolm(struct bus *bus) |
| 39 | { |
| 40 | struct resource *min; |
| 41 | uint32_t tolm; |
| 42 | min = 0; |
| 43 | search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); |
| 44 | tolm = 0xffffffffUL; |
| 45 | if (min && tolm > min->base) { |
| 46 | tolm = min->base; |
| 47 | } |
| 48 | return tolm; |
| 49 | } |
Stefan Reinauer | e4932dc | 2004-11-02 20:33:12 +0000 | [diff] [blame] | 50 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame^] | 51 | #if CONFIG_WRITE_HIGH_TABLES==1 |
Myles Watson | 0520d55 | 2009-05-11 22:44:14 +0000 | [diff] [blame] | 52 | #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB |
| 53 | extern uint64_t high_tables_base, high_tables_size; |
| 54 | #endif |
| 55 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 56 | static void cpu_pci_domain_set_resources(device_t dev) |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 57 | { |
Ronald G. Minnich | 9cf642b | 2006-09-13 04:12:35 +0000 | [diff] [blame] | 58 | static const uint8_t ramregs[] = { |
| 59 | 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 |
| 60 | }; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 61 | device_t mc_dev; |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 62 | uint32_t pci_tolm; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 63 | |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 64 | pci_tolm = find_pci_tolm(&dev->link[0]); |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 65 | mc_dev = dev->link[0].children; |
| 66 | if (mc_dev) { |
| 67 | unsigned long tomk, tolmk; |
Ronald G. Minnich | 9cf642b | 2006-09-13 04:12:35 +0000 | [diff] [blame] | 68 | unsigned char rambits; |
| 69 | int i, idx; |
| 70 | |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 71 | for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { |
Ronald G. Minnich | 9cf642b | 2006-09-13 04:12:35 +0000 | [diff] [blame] | 72 | unsigned char reg; |
| 73 | reg = pci_read_config8(mc_dev, ramregs[i]); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 74 | /* these are ENDING addresses, not sizes. |
Ronald G. Minnich | 9cf642b | 2006-09-13 04:12:35 +0000 | [diff] [blame] | 75 | * if there is memory in this slot, then reg will be > rambits. |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 76 | * So we just take the max, that gives us total. |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 77 | * We take the highest one to cover for once and future coreboot |
Ronald G. Minnich | 9cf642b | 2006-09-13 04:12:35 +0000 | [diff] [blame] | 78 | * bugs. We warn about bugs. |
| 79 | */ |
| 80 | if (reg > rambits) |
| 81 | rambits = reg; |
| 82 | if (reg < rambits) |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 83 | printk_err("ERROR! register 0x%x is not set!\n", |
Ronald G. Minnich | 9cf642b | 2006-09-13 04:12:35 +0000 | [diff] [blame] | 84 | ramregs[i]); |
| 85 | } |
| 86 | if (rambits == 0) { |
| 87 | printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n"); |
| 88 | rambits = 8; |
| 89 | } |
| 90 | printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); |
| 91 | tomk = rambits*8*1024; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 92 | /* Compute the top of Low memory */ |
| 93 | tolmk = pci_tolm >> 10; |
| 94 | if (tolmk >= tomk) { |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 95 | /* The PCI hole does not overlap the memory. */ |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 96 | tolmk = tomk; |
| 97 | } |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 98 | |
| 99 | /* Report the memory regions. */ |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 100 | idx = 10; |
Myles Watson | 0520d55 | 2009-05-11 22:44:14 +0000 | [diff] [blame] | 101 | ram_resource(dev, idx++, 0, 640); |
| 102 | ram_resource(dev, idx++, 768, tolmk - 768); |
| 103 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame^] | 104 | #if CONFIG_WRITE_HIGH_TABLES==1 |
Myles Watson | 0520d55 | 2009-05-11 22:44:14 +0000 | [diff] [blame] | 105 | /* Leave some space for ACPI, PIRQ and MP tables */ |
| 106 | high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; |
| 107 | high_tables_size = HIGH_TABLES_SIZE * 1024; |
| 108 | #endif |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 109 | } |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 110 | assign_resources(&dev->link[0]); |
| 111 | } |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 112 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 113 | static void cpu_pci_domain_read_resources(struct device *dev) |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 114 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 115 | struct resource *res; |
| 116 | |
| 117 | pci_domain_read_resources(dev); |
| 118 | |
| 119 | /* Reserve space for the IOAPIC. This should be in the Southbridge, |
| 120 | * but I couldn't tell which device to put it in. */ |
| 121 | res = new_resource(dev, 2); |
| 122 | res->base = 0xfec00000UL; |
| 123 | res->size = 0x100000UL; |
| 124 | res->limit = 0xffffffffUL; |
| 125 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 126 | IORESOURCE_ASSIGNED; |
| 127 | |
| 128 | /* Reserve space for the LAPIC. There's one in every processor, but |
| 129 | * the space only needs to be reserved once, so we do it here. */ |
| 130 | res = new_resource(dev, 3); |
| 131 | res->base = 0xfee00000UL; |
| 132 | res->size = 0x10000UL; |
| 133 | res->limit = 0xffffffffUL; |
| 134 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 135 | IORESOURCE_ASSIGNED; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static struct device_operations pci_domain_ops = { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 139 | .read_resources = cpu_pci_domain_read_resources, |
| 140 | .set_resources = cpu_pci_domain_set_resources, |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 141 | .enable_resources = enable_childrens_resources, |
| 142 | .init = 0, |
| 143 | .scan_bus = pci_domain_scan_bus, |
| 144 | }; |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 145 | |
| 146 | static void enable_dev(struct device *dev) |
| 147 | { |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 148 | /* Set the operations if it is a special bus type */ |
| 149 | if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { |
| 150 | dev->ops = &pci_domain_ops; |
Eric Biederman | a9e632c | 2004-11-18 22:38:08 +0000 | [diff] [blame] | 151 | pci_set_method(dev); |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 152 | } |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 153 | } |
| 154 | |
Myles Watson | b8c2aa2 | 2008-02-07 20:37:37 +0000 | [diff] [blame] | 155 | struct chip_operations cpu_emulation_qemu_x86_ops = { |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 156 | CHIP_NAME("QEMU Northbridge") |
Eric Biederman | 6e53f50 | 2004-10-27 08:53:57 +0000 | [diff] [blame] | 157 | .enable_dev = enable_dev, |
Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame] | 158 | }; |
Stefan Reinauer | 246ae21 | 2005-09-08 17:17:25 +0000 | [diff] [blame] | 159 | |
| 160 | void udelay(int usecs) |
| 161 | { |
| 162 | int i; |
| 163 | for(i = 0; i < usecs; i++) |
Stefan Reinauer | 8e65adb | 2008-08-13 12:16:15 +0000 | [diff] [blame] | 164 | inb(0x80); |
Stefan Reinauer | 246ae21 | 2005-09-08 17:17:25 +0000 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | |