| Stefan Reinauer | e2b53e1 | 2004-06-28 11:59:45 +0000 | [diff] [blame^] | 1 | #include <console/console.h> |
| 2 | #include <arch/io.h> |
| 3 | #include <stdint.h> |
| 4 | #include <mem.h> |
| 5 | #include <part/sizeram.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/hypertransport.h> |
| 9 | #include <device/chip.h> |
| 10 | #include <stdlib.h> |
| 11 | #include <string.h> |
| 12 | #include <bitops.h> |
| 13 | #include "chip.h" |
| 14 | #include "northbridge.h" |
| 15 | |
| 16 | void hard_reset(void) |
| 17 | { |
| 18 | printk_err("Hard_RESET!!!\n"); |
| 19 | } |
| 20 | |
| 21 | struct mem_range *sizeram(void) |
| 22 | { |
| 23 | unsigned long mmio_basek; |
| 24 | static struct mem_range mem[10]; |
| 25 | device_t dev; |
| 26 | int i, idx; |
| 27 | unsigned char rambits; |
| 28 | |
| 29 | dev = dev_find_slot(0, 0); |
| 30 | if (!dev) { |
| 31 | printk_err("Cannot find PCI: 0:0\n"); |
| 32 | return 0; |
| 33 | } |
| 34 | mem[0].basek = 0; |
| 35 | mem[0].sizek = 65536; |
| 36 | #if 0 |
| 37 | idx = 1; |
| 38 | while(idx < sizeof(mem)/sizeof(mem[0])) { |
| 39 | mem[idx].basek = 0; |
| 40 | mem[idx].sizek = 0; |
| 41 | idx++; |
| 42 | } |
| 43 | for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { |
| 44 | unsigned char reg; |
| 45 | reg = pci_read_config8(dev, ramregs[i]); |
| 46 | /* these are ENDING addresses, not sizes. |
| 47 | * if there is memory in this slot, then reg will be > rambits. |
| 48 | * So we just take the max, that gives us total. |
| 49 | * We take the highest one to cover for once and future linuxbios |
| 50 | * bugs. We warn about bugs. |
| 51 | */ |
| 52 | if (reg > rambits) |
| 53 | rambits = reg; |
| 54 | if (reg < rambits) |
| 55 | printk_err("ERROR! register 0x%x is not set!\n", |
| 56 | ramregs[i]); |
| 57 | } |
| 58 | |
| 59 | printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); |
| 60 | mem[0].sizek = rambits*8*1024; |
| 61 | #endif |
| 62 | #if 1 |
| 63 | for(i = 0; i < idx; i++) { |
| 64 | printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n", |
| 65 | i, mem[i].basek, i, mem[i].sizek); |
| 66 | } |
| 67 | #endif |
| 68 | |
| 69 | return mem; |
| 70 | } |
| 71 | |
| 72 | static void enumerate(struct chip *chip) |
| 73 | { |
| 74 | extern struct device_operations default_pci_ops_bus; |
| 75 | chip_enumerate(chip); |
| 76 | chip->dev->ops = &default_pci_ops_bus; |
| 77 | } |
| 78 | |
| 79 | static void random_fixup() { |
| 80 | device_t pcidev = dev_find_slot(0, 0); |
| 81 | |
| 82 | printk_warning("QEMU random fixup ...\n"); |
| 83 | if (pcidev) { |
| 84 | // pci_write_config8(pcidev, 0x0, 0x0); |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | static void northbridge_init(struct chip *chip, enum chip_pass pass) |
| 89 | { |
| 90 | |
| 91 | struct northbridge_dummy_qemu_i386_config *conf = |
| 92 | (struct northbridge_dummy_qemu_i386_config *)chip->chip_info; |
| 93 | |
| 94 | switch (pass) { |
| 95 | case CONF_PASS_PRE_PCI: |
| 96 | break; |
| 97 | |
| 98 | case CONF_PASS_POST_PCI: |
| 99 | break; |
| 100 | |
| 101 | case CONF_PASS_PRE_BOOT: |
| 102 | random_fixup(); |
| 103 | break; |
| 104 | |
| 105 | default: |
| 106 | /* nothing yet */ |
| 107 | break; |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | struct chip_control northbridge_emulation_qemu_i386_control = { |
| 112 | .enumerate = enumerate, |
| 113 | .enable = northbridge_init, |
| 114 | .name = "QEMU Northbridge", |
| 115 | }; |