Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
| 3 | #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 4 | #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 5 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 6 | /* Device ID for SandyBridge and IvyBridge */ |
| 7 | #define BASE_REV_SNB 0x00 |
| 8 | #define BASE_REV_IVB 0x50 |
| 9 | #define BASE_REV_MASK 0x50 |
| 10 | |
| 11 | /* SandyBridge CPU stepping */ |
| 12 | #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ |
| 13 | #define SNB_STEP_D1 (BASE_REV_SNB + 6) |
| 14 | #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ |
| 15 | |
| 16 | /* IvyBridge CPU stepping */ |
| 17 | #define IVB_STEP_A0 (BASE_REV_IVB + 0) |
| 18 | #define IVB_STEP_B0 (BASE_REV_IVB + 2) |
| 19 | #define IVB_STEP_C0 (BASE_REV_IVB + 4) |
| 20 | #define IVB_STEP_K0 (BASE_REV_IVB + 5) |
| 21 | #define IVB_STEP_D0 (BASE_REV_IVB + 6) |
| 22 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 23 | /* Northbridge BARs */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 24 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 25 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
| 26 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 27 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 28 | #define GFXVT_BASE 0xfed90000ULL |
| 29 | #define VTVC0_BASE 0xfed91000ULL |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 30 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 31 | /* Everything below this line is ignored in the DSDT */ |
| 32 | #ifndef __ACPI__ |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 33 | #include <stdint.h> |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 34 | |
| 35 | /* Chipset types */ |
| 36 | enum platform_type { |
| 37 | PLATFORM_MOBILE = 0, |
| 38 | PLATFORM_DESKTOP_SERVER, |
| 39 | }; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 40 | |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 41 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 42 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 43 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 44 | |
Angel Pons | 579e096 | 2020-07-22 11:11:50 +0200 | [diff] [blame] | 45 | #include "hostbridge_regs.h" |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 46 | |
| 47 | |
| 48 | /* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ |
| 49 | |
| 50 | #define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */ |
| 51 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 52 | |
| 53 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 54 | |
| 55 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 56 | |
| 57 | /* |
| 58 | * MCHBAR |
| 59 | */ |
| 60 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 61 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
Felix Held | b9267f0 | 2018-07-28 14:49:31 +0200 | [diff] [blame] | 62 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
Angel Pons | 7431593 | 2020-09-14 16:50:49 +0200 | [diff] [blame^] | 63 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 64 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 65 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 66 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 67 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 68 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 69 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 70 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 71 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
Angel Pons | 26be0bd | 2019-12-31 14:29:48 +0100 | [diff] [blame] | 72 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 73 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 74 | /* As there are many registers, define them on a separate file */ |
| 75 | #include "mchbar_regs.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * EPBAR - Egress Port Root Complex Register Block |
| 79 | */ |
| 80 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 81 | #define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) |
Felix Held | b9267f0 | 2018-07-28 14:49:31 +0200 | [diff] [blame] | 82 | #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) |
| 83 | #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 84 | |
| 85 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 86 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 87 | |
| 88 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 89 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 90 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 91 | |
| 92 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 93 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 94 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 95 | |
| 96 | #define EPVC1MTS 0x028 /* 32bit */ |
| 97 | #define EPVC1IST 0x038 /* 64bit */ |
| 98 | |
| 99 | #define EPESD 0x044 /* 32bit */ |
| 100 | |
| 101 | #define EPLE1D 0x050 /* 32bit */ |
| 102 | #define EPLE1A 0x058 /* 64bit */ |
| 103 | #define EPLE2D 0x060 /* 32bit */ |
| 104 | #define EPLE2A 0x068 /* 64bit */ |
| 105 | |
| 106 | #define PORTARB 0x100 /* 256bit */ |
| 107 | |
| 108 | /* |
| 109 | * DMIBAR |
| 110 | */ |
| 111 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 112 | #define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) |
Felix Held | b9267f0 | 2018-07-28 14:49:31 +0200 | [diff] [blame] | 113 | #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) |
| 114 | #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 115 | |
| 116 | #define DMIVCECH 0x000 /* 32bit */ |
| 117 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 118 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 119 | |
| 120 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 121 | |
| 122 | #define DMIVC0RCAP 0x010 /* 32bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 123 | #define DMIVC0RCTL 0x014 /* 32bit */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 124 | #define DMIVC0RSTS 0x01a /* 16bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 125 | #define VC0NP 0x2 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 126 | |
| 127 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 128 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 129 | #define DMIVC1RSTS 0x026 /* 16bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 130 | #define VC1NP 0x2 |
| 131 | |
| 132 | #define DMIVCPRCTL 0x02c /* 32bit */ |
| 133 | |
| 134 | #define DMIVCPRSTS 0x032 /* 16bit */ |
| 135 | #define VCPNP 0x2 |
| 136 | |
| 137 | #define DMIVCMRCTL 0x0038 /* 32 bit */ |
| 138 | #define DMIVCMRSTS 0x003e /* 16 bit */ |
| 139 | #define VCMNP 0x2 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 140 | |
| 141 | #define DMILE1D 0x050 /* 32bit */ |
| 142 | #define DMILE1A 0x058 /* 64bit */ |
| 143 | #define DMILE2D 0x060 /* 32bit */ |
| 144 | #define DMILE2A 0x068 /* 64bit */ |
| 145 | |
| 146 | #define DMILCAP 0x084 /* 32bit */ |
| 147 | #define DMILCTL 0x088 /* 16bit */ |
| 148 | #define DMILSTS 0x08a /* 16bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 149 | #define TXTRN (1 << 11) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 150 | #define DMICTL1 0x0f0 /* 32bit */ |
| 151 | #define DMICTL2 0x0fc /* 32bit */ |
| 152 | |
| 153 | #define DMICC 0x208 /* 32bit */ |
| 154 | |
| 155 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 156 | |
| 157 | #ifndef __ASSEMBLER__ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 158 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 159 | void intel_sandybridge_finalize_smm(void); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 160 | int bridge_silicon_revision(void); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 161 | void systemagent_early_init(void); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 162 | void sandybridge_init_iommu(void); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 163 | void sandybridge_late_initialization(void); |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 164 | void northbridge_romstage_finalize(int s3resume); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 165 | void early_init_dmi(void); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 166 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 167 | /* mainboard_early_init: Optional callback, run after console init but before raminit. */ |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 168 | void mainboard_early_init(int s3resume); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 169 | int mainboard_should_reset_usb(int s3resume); |
| 170 | void perform_raminit(int s3resume); |
Angel Pons | 064c799 | 2020-03-17 23:09:16 +0100 | [diff] [blame] | 171 | void report_memory_config(void); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 172 | enum platform_type get_platform_type(void); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 173 | |
Angel Pons | 8bf1976 | 2020-08-03 14:55:18 +0200 | [diff] [blame] | 174 | int decode_pcie_bar(u32 *const base, u32 *const len); |
| 175 | |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 176 | #include <device/device.h> |
| 177 | |
| 178 | struct acpi_rsdp; |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 179 | unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 180 | struct acpi_rsdp *rsdp); |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 181 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 182 | #endif |
| 183 | #endif |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 184 | #endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ |