Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2015-2016 Intel Corp. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
| 16 | config SOC_INTEL_QUARK |
| 17 | bool |
| 18 | help |
| 19 | Intel Quark support |
| 20 | |
| 21 | if SOC_INTEL_QUARK |
| 22 | |
| 23 | config CPU_SPECIFIC_OPTIONS |
| 24 | def_bool y |
| 25 | select ARCH_BOOTBLOCK_X86_32 |
| 26 | select ARCH_RAMSTAGE_X86_32 |
| 27 | select ARCH_ROMSTAGE_X86_32 |
| 28 | select ARCH_VERSTAGE_X86_32 |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 29 | select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP |
| 30 | select C_ENVIRONMENT_BOOTBLOCK |
Lee Leahy | 6e8233a | 2016-07-30 10:34:22 -0700 | [diff] [blame] | 31 | select HAVE_HARD_RESET |
Lee Leahy | 73f6a28 | 2016-12-28 12:53:37 -0800 | [diff] [blame^] | 32 | select NO_MMCONF_SUPPORT |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 33 | select REG_SCRIPT |
Lee Leahy | d87d8ea | 2016-07-21 14:14:02 -0700 | [diff] [blame] | 34 | select RELOCATABLE_RAMSTAGE |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 35 | select SOC_INTEL_COMMON |
Lee Leahy | 6e8233a | 2016-07-30 10:34:22 -0700 | [diff] [blame] | 36 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 37 | select SOC_SETS_MSRS |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 38 | select TSC_CONSTANT_RATE |
Lee Leahy | 6ec72c9 | 2016-05-07 09:04:46 -0700 | [diff] [blame] | 39 | select UART_OVERRIDE_REFCLK |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 40 | select UDELAY_TSC |
Lee Leahy | 43cdff6 | 2016-02-07 14:52:22 -0800 | [diff] [blame] | 41 | select UNCOMPRESSED_RAMSTAGE |
Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 42 | select USE_MARCH_586 |
| 43 | |
Lee Leahy | 73f6a28 | 2016-12-28 12:53:37 -0800 | [diff] [blame^] | 44 | config MMCOMF_SUPPORT_DEFAULT |
| 45 | bool |
| 46 | default n |
| 47 | |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 48 | ##### |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 49 | # Debug serial output |
| 50 | # The following options configure the debug serial port |
| 51 | ##### |
| 52 | |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 53 | config ENABLE_BUILTIN_HSUART0 |
| 54 | bool "Enable built-in HSUART0" |
| 55 | default n |
| 56 | select NO_UART_ON_SUPERIO |
| 57 | select DRIVERS_UART_8250MEM_32 |
| 58 | help |
| 59 | The Quark SoC has two HSUART. Choose this option to configure the pads |
| 60 | and enable HSUART0, which can be used for the debug console. |
| 61 | |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 62 | config ENABLE_BUILTIN_HSUART1 |
| 63 | bool "Enable built-in HSUART1" |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 64 | default n |
| 65 | depends on ! ENABLE_BUILTIN_HSUART0 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 66 | select NO_UART_ON_SUPERIO |
| 67 | select DRIVERS_UART_8250MEM_32 |
| 68 | help |
| 69 | The Quark SoC has two HSUART. Choose this option to configure the pads |
| 70 | and enable HSUART1, which can be used for the debug console. |
| 71 | |
| 72 | config TTYS0_BASE |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 73 | hex "HSUART Base Address" |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 74 | default 0xA0019000 |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 75 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 76 | help |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 77 | Memory mapped MMIO of HSUART. |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 78 | |
| 79 | config TTYS0_LCS |
| 80 | int |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 81 | default 3 |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 82 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 83 | |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 84 | # Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12 |
Lee Leahy | 614ef40 | 2016-05-04 12:50:51 -0700 | [diff] [blame] | 85 | # Valid bit, PCI UART in use: 1 << 31 |
| 86 | config UART_PCI_ADDR |
| 87 | hex |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 88 | default 0x800a1000 if ENABLE_BUILTIN_HSUART0 |
| 89 | default 0x800a5000 if ENABLE_BUILTIN_HSUART1 |
| 90 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 614ef40 | 2016-05-04 12:50:51 -0700 | [diff] [blame] | 91 | |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 92 | ##### |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 93 | # Debug support |
| 94 | # The following options provide debug support for the Quark coreboot |
| 95 | # code. The SD LED is used as a binary marker to determine if a |
| 96 | # specific point in the execution flow has been reached. |
| 97 | ##### |
| 98 | |
| 99 | config ENABLE_DEBUG_LED |
| 100 | bool |
| 101 | default n |
| 102 | help |
| 103 | Enable the use of the SD LED for early debugging before serial output |
| 104 | is available. Setting this LED indicates that control has reached the |
| 105 | desired check point. |
| 106 | |
| 107 | config ENABLE_DEBUG_LED_ESRAM |
| 108 | bool "SD LED indicates ESRAM initialized" |
| 109 | default n |
| 110 | select ENABLE_DEBUG_LED |
| 111 | help |
| 112 | Indicate that ESRAM has been successfully initialized. |
| 113 | |
| 114 | config ENABLE_DEBUG_LED_FINDFSP |
| 115 | bool "SD LED indicates fsp.bin file was found" |
| 116 | default n |
| 117 | select ENABLE_DEBUG_LED |
| 118 | help |
| 119 | Indicate that fsp.bin was found. |
| 120 | |
| 121 | config ENABLE_DEBUG_LED_TEMPRAMINIT |
| 122 | bool "SD LED indicates TempRamInit was successful" |
| 123 | default n |
| 124 | select ENABLE_DEBUG_LED |
| 125 | help |
| 126 | Indicate that TempRamInit was successful. |
| 127 | |
| 128 | ##### |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 129 | # ESRAM layout |
| 130 | # Specify the portion of the ESRAM for coreboot to use as its data area. |
| 131 | ##### |
| 132 | |
| 133 | config DCACHE_RAM_BASE |
| 134 | hex |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 135 | default 0x80070000 if PLATFORM_USES_FSP1_1 |
| 136 | default 0x80000000 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 137 | |
| 138 | config DCACHE_RAM_SIZE |
| 139 | hex |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 140 | default 0x8000 if PLATFORM_USES_FSP1_1 |
| 141 | default 0x40000 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 142 | |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 143 | config DISPLAY_ESRAM_LAYOUT |
| 144 | bool "Display ESRAM layout" |
| 145 | default n |
| 146 | depends on PLATFORM_USES_FSP2_0 |
| 147 | help |
| 148 | Select this option to display coreboot's use of ESRAM. |
| 149 | |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 150 | ##### |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 151 | # Flash layout |
| 152 | # Specify the size of the coreboot file system in the read-only |
| 153 | # (recovery) portion of the flash part. |
| 154 | ##### |
| 155 | |
| 156 | config CBFS_SIZE |
| 157 | hex |
| 158 | default 0x200000 |
| 159 | help |
| 160 | Specify the size of the coreboot file system in the read-only (recovery) |
| 161 | portion of the flash part. On Quark systems the firmware image stores |
| 162 | more than just coreboot, including: |
| 163 | - The chipset microcode (RMU) binary file located at 0xFFF00000 |
| 164 | - Intel Trusted Execution Engine firmware |
| 165 | |
| 166 | ##### |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 167 | # FSP binary |
| 168 | # The following options control the FSP binary file placement in |
| 169 | # the flash image and ESRAM. This file is required by the Quark |
| 170 | # SoC code to boot coreboot and its payload. |
| 171 | ##### |
| 172 | |
| 173 | config ADD_FSP_RAW_BIN |
| 174 | bool "Add the Intel FSP binary to the flash image without relocation" |
| 175 | default n |
| 176 | depends on PLATFORM_USES_FSP1_1 |
| 177 | help |
| 178 | Select this option to add an Intel FSP binary to |
| 179 | the resulting coreboot image. |
| 180 | |
| 181 | Note: Without this binary, coreboot builds relying on the FSP |
| 182 | will not boot |
| 183 | |
| 184 | config FSP_FILE |
| 185 | string "Intel FSP binary path and filename" |
Lee Leahy | 54f857b | 2016-09-28 18:03:13 -0700 | [diff] [blame] | 186 | default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP.fd" |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 187 | depends on PLATFORM_USES_FSP1_1 |
| 188 | depends on ADD_FSP_RAW_BIN |
| 189 | help |
| 190 | The path and filename of the Intel FSP binary for this platform. |
| 191 | |
| 192 | config FSP_IMAGE_ID_STRING |
| 193 | string "8 byte platform string identifying the FSP platform" |
| 194 | default "QUK-FSP0" |
| 195 | depends on PLATFORM_USES_FSP1_1 |
| 196 | help |
| 197 | 8 ASCII character byte signature string that will help match the FSP |
| 198 | binary to a supported hardware configuration. |
| 199 | |
| 200 | config FSP_LOC |
| 201 | hex |
| 202 | default 0xfff80000 |
| 203 | depends on PLATFORM_USES_FSP1_1 |
| 204 | help |
| 205 | The location in CBFS that the FSP is located. This must match the |
| 206 | value that is set in the FSP binary. If the FSP needs to be moved, |
| 207 | rebase the FSP with Intel's BCT (tool). |
| 208 | |
| 209 | config FSP_ESRAM_LOC |
| 210 | hex |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 211 | default 0x80000000 if PLATFORM_USES_FSP1_1 |
| 212 | default 0x80040000 |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 213 | help |
| 214 | The location in ESRAM where a copy of the FSP binary is placed. |
| 215 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 216 | config RELOCATE_FSP_INTO_DRAM |
| 217 | bool "Relocate FSP into DRAM" |
| 218 | default n |
| 219 | depends on PLATFORM_USES_FSP1_1 |
| 220 | help |
| 221 | Relocate the FSP binary into DRAM before the call to SiliconInit. |
| 222 | |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 223 | config FSP_M_FILE |
| 224 | string |
| 225 | depends on PLATFORM_USES_FSP2_0 |
Lee Leahy | 54f857b | 2016-09-28 18:03:13 -0700 | [diff] [blame] | 226 | default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd" |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 227 | |
| 228 | config FSP_S_FILE |
| 229 | string |
| 230 | depends on PLATFORM_USES_FSP2_0 |
Lee Leahy | 54f857b | 2016-09-28 18:03:13 -0700 | [diff] [blame] | 231 | default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd" |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 232 | |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 233 | ##### |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 234 | # RMU binary |
| 235 | # The following options control the Quark chipset microcode file |
| 236 | # placement in the flash image. This file is required to bring |
| 237 | # the Quark processor out of reset. |
| 238 | ##### |
| 239 | |
| 240 | config ADD_RMU_FILE |
| 241 | bool "Should the RMU binary be added to the flash image?" |
| 242 | default n |
| 243 | help |
| 244 | The RMU file is required to get the chip out of reset. |
| 245 | |
| 246 | config RMU_FILE |
| 247 | string |
| 248 | default "3rdparty/blobs/soc/intel/quark/rmu.bin" |
| 249 | depends on ADD_RMU_FILE |
| 250 | help |
| 251 | The path and filename of the Intel Quark RMU binary. |
| 252 | |
| 253 | config RMU_LOC |
| 254 | hex |
| 255 | default 0xfff00000 |
| 256 | depends on ADD_RMU_FILE |
| 257 | help |
| 258 | The location in CBFS that the RMU is located. It must match the |
| 259 | strap-determined base address. |
| 260 | |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 261 | ##### |
| 262 | # Bootblock |
| 263 | # The following options support the C_ENVIRONMENT_BOOTBLOCK. |
| 264 | ##### |
| 265 | |
| 266 | config DCACHE_BSP_STACK_SIZE |
| 267 | hex |
| 268 | default 0x4000 |
| 269 | |
| 270 | config C_ENV_BOOTBLOCK_SIZE |
| 271 | hex |
| 272 | default 0x8000 |
| 273 | |
Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 274 | endif # SOC_INTEL_QUARK |