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Lee Leahy2ed7eb72016-01-01 18:08:48 -08001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2015-2016 Intel Corp.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15
16config SOC_INTEL_QUARK
17 bool
18 help
19 Intel Quark support
20
21if SOC_INTEL_QUARK
22
23config CPU_SPECIFIC_OPTIONS
24 def_bool y
25 select ARCH_BOOTBLOCK_X86_32
26 select ARCH_RAMSTAGE_X86_32
27 select ARCH_ROMSTAGE_X86_32
28 select ARCH_VERSTAGE_X86_32
Lee Leahy4dd34ee2016-05-02 14:31:02 -070029 select REG_SCRIPT
Lee Leahy87df8d02016-02-07 14:37:13 -080030 select SOC_INTEL_COMMON
Lee Leahy43cdff62016-02-07 14:52:22 -080031 select SOC_SETS_MTRRS
Lee Leahy87df8d02016-02-07 14:37:13 -080032 select TSC_CONSTANT_RATE
33 select UDELAY_TSC
Lee Leahy43cdff62016-02-07 14:52:22 -080034 select UNCOMPRESSED_RAMSTAGE
Lee Leahy2ed7eb72016-01-01 18:08:48 -080035 select USE_MARCH_586
36
Lee Leahy9fd08952016-02-02 07:17:06 -080037#####
Lee Leahy87df8d02016-02-07 14:37:13 -080038# Debug serial output
39# The following options configure the debug serial port
40#####
41
42config ENABLE_BUILTIN_HSUART1
43 bool "Enable built-in HSUART1"
44 default y
45 select NO_UART_ON_SUPERIO
46 select DRIVERS_UART_8250MEM_32
47 help
48 The Quark SoC has two HSUART. Choose this option to configure the pads
49 and enable HSUART1, which can be used for the debug console.
50
51config TTYS0_BASE
52 hex "HSUART1 Base Address"
53 depends on ENABLE_BUILTIN_HSUART1
54 default 0xA0019000
55 help
56 Memory mapped MMIO of HSUART1.
57
58config TTYS0_LCS
59 int
60 depends on ENABLE_BUILTIN_HSUART1
61 default 3
62
63#####
Lee Leahya7ba56e2016-02-07 10:42:14 -080064# Debug support
65# The following options provide debug support for the Quark coreboot
66# code. The SD LED is used as a binary marker to determine if a
67# specific point in the execution flow has been reached.
68#####
69
70config ENABLE_DEBUG_LED
71 bool
72 default n
73 help
74 Enable the use of the SD LED for early debugging before serial output
75 is available. Setting this LED indicates that control has reached the
76 desired check point.
77
78config ENABLE_DEBUG_LED_ESRAM
79 bool "SD LED indicates ESRAM initialized"
80 default n
81 select ENABLE_DEBUG_LED
82 help
83 Indicate that ESRAM has been successfully initialized.
84
85config ENABLE_DEBUG_LED_FINDFSP
86 bool "SD LED indicates fsp.bin file was found"
87 default n
88 select ENABLE_DEBUG_LED
89 help
90 Indicate that fsp.bin was found.
91
92config ENABLE_DEBUG_LED_TEMPRAMINIT
93 bool "SD LED indicates TempRamInit was successful"
94 default n
95 select ENABLE_DEBUG_LED
96 help
97 Indicate that TempRamInit was successful.
98
99#####
Lee Leahy87df8d02016-02-07 14:37:13 -0800100# ESRAM layout
101# Specify the portion of the ESRAM for coreboot to use as its data area.
102#####
103
104config DCACHE_RAM_BASE
105 hex
106 default 0x80070000
107
108config DCACHE_RAM_SIZE
109 hex
110 default 0x00008000
111
112#####
Lee Leahy9fd08952016-02-02 07:17:06 -0800113# Flash layout
114# Specify the size of the coreboot file system in the read-only
115# (recovery) portion of the flash part.
116#####
117
118config CBFS_SIZE
119 hex
120 default 0x200000
121 help
122 Specify the size of the coreboot file system in the read-only (recovery)
123 portion of the flash part. On Quark systems the firmware image stores
124 more than just coreboot, including:
125 - The chipset microcode (RMU) binary file located at 0xFFF00000
126 - Intel Trusted Execution Engine firmware
127
128#####
Lee Leahya7ba56e2016-02-07 10:42:14 -0800129# FSP binary
130# The following options control the FSP binary file placement in
131# the flash image and ESRAM. This file is required by the Quark
132# SoC code to boot coreboot and its payload.
133#####
134
135config ADD_FSP_RAW_BIN
136 bool "Add the Intel FSP binary to the flash image without relocation"
137 default n
138 depends on PLATFORM_USES_FSP1_1
139 help
140 Select this option to add an Intel FSP binary to
141 the resulting coreboot image.
142
143 Note: Without this binary, coreboot builds relying on the FSP
144 will not boot
145
146config FSP_FILE
147 string "Intel FSP binary path and filename"
148 default "3rdparty/blobs/soc/intel/quark/fsp.bin"
149 depends on PLATFORM_USES_FSP1_1
150 depends on ADD_FSP_RAW_BIN
151 help
152 The path and filename of the Intel FSP binary for this platform.
153
154config FSP_IMAGE_ID_STRING
155 string "8 byte platform string identifying the FSP platform"
156 default "QUK-FSP0"
157 depends on PLATFORM_USES_FSP1_1
158 help
159 8 ASCII character byte signature string that will help match the FSP
160 binary to a supported hardware configuration.
161
162config FSP_LOC
163 hex
164 default 0xfff80000
165 depends on PLATFORM_USES_FSP1_1
166 help
167 The location in CBFS that the FSP is located. This must match the
168 value that is set in the FSP binary. If the FSP needs to be moved,
169 rebase the FSP with Intel's BCT (tool).
170
171config FSP_ESRAM_LOC
172 hex
173 default 0x80000000
174 depends on PLATFORM_USES_FSP1_1
175 help
176 The location in ESRAM where a copy of the FSP binary is placed.
177
Lee Leahyd4edacb2016-02-08 07:12:30 -0800178config RELOCATE_FSP_INTO_DRAM
179 bool "Relocate FSP into DRAM"
180 default n
181 depends on PLATFORM_USES_FSP1_1
182 help
183 Relocate the FSP binary into DRAM before the call to SiliconInit.
184
Lee Leahya7ba56e2016-02-07 10:42:14 -0800185#####
186# FSP PDAT binary
187# The following options control the FSP platform data binary
188# file placement in the flash image.
189#####
190
191config ADD_FSP_PDAT_FILE
192 bool "Should the PDAT binary be added to the flash image?"
193 default n
194 depends on PLATFORM_USES_FSP1_1
195 help
196 The PDAT file is required for the FSP 1.1 binary
197
198config FSP_PDAT_FILE
199 string
200 default "3rdparty/blobs/soc/intel/quark/pdat.bin"
201 depends on PLATFORM_USES_FSP1_1
202 depends on ADD_FSP_PDAT_FILE
203 help
204 The path and filename of the Intel Galileo platform-data-patch (PDAT)
205 binary. This binary file is generated by the platform-data-patch.py
206 script released with the Quark BSP and contains the Ethernet address.
207
208config FSP_PDAT_LOC
209 hex
210 default 0xfff10000
211 depends on PLATFORM_USES_FSP1_1
212 depends on ADD_FSP_PDAT_FILE
213 help
214 The location in CBFS that the PDAT is located. It must match the
215 PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
216
217#####
Lee Leahy9fd08952016-02-02 07:17:06 -0800218# RMU binary
219# The following options control the Quark chipset microcode file
220# placement in the flash image. This file is required to bring
221# the Quark processor out of reset.
222#####
223
224config ADD_RMU_FILE
225 bool "Should the RMU binary be added to the flash image?"
226 default n
227 help
228 The RMU file is required to get the chip out of reset.
229
230config RMU_FILE
231 string
232 default "3rdparty/blobs/soc/intel/quark/rmu.bin"
233 depends on ADD_RMU_FILE
234 help
235 The path and filename of the Intel Quark RMU binary.
236
237config RMU_LOC
238 hex
239 default 0xfff00000
240 depends on ADD_RMU_FILE
241 help
242 The location in CBFS that the RMU is located. It must match the
243 strap-determined base address.
244
Lee Leahy2ed7eb72016-01-01 18:08:48 -0800245endif # SOC_INTEL_QUARK