Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2015-2016 Intel Corp. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
| 16 | config SOC_INTEL_QUARK |
| 17 | bool |
| 18 | help |
| 19 | Intel Quark support |
| 20 | |
| 21 | if SOC_INTEL_QUARK |
| 22 | |
| 23 | config CPU_SPECIFIC_OPTIONS |
| 24 | def_bool y |
| 25 | select ARCH_BOOTBLOCK_X86_32 |
| 26 | select ARCH_RAMSTAGE_X86_32 |
| 27 | select ARCH_ROMSTAGE_X86_32 |
| 28 | select ARCH_VERSTAGE_X86_32 |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 29 | select REG_SCRIPT |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 30 | select SOC_INTEL_COMMON |
Lee Leahy | 43cdff6 | 2016-02-07 14:52:22 -0800 | [diff] [blame] | 31 | select SOC_SETS_MTRRS |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 32 | select TSC_CONSTANT_RATE |
Lee Leahy | 6ec72c9 | 2016-05-07 09:04:46 -0700 | [diff] [blame] | 33 | select UART_OVERRIDE_REFCLK |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 34 | select UDELAY_TSC |
Lee Leahy | 43cdff6 | 2016-02-07 14:52:22 -0800 | [diff] [blame] | 35 | select UNCOMPRESSED_RAMSTAGE |
Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 36 | select USE_MARCH_586 |
| 37 | |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 38 | ##### |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 39 | # Debug serial output |
| 40 | # The following options configure the debug serial port |
| 41 | ##### |
| 42 | |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 43 | config ENABLE_BUILTIN_HSUART0 |
| 44 | bool "Enable built-in HSUART0" |
| 45 | default n |
| 46 | select NO_UART_ON_SUPERIO |
| 47 | select DRIVERS_UART_8250MEM_32 |
| 48 | help |
| 49 | The Quark SoC has two HSUART. Choose this option to configure the pads |
| 50 | and enable HSUART0, which can be used for the debug console. |
| 51 | |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 52 | config ENABLE_BUILTIN_HSUART1 |
| 53 | bool "Enable built-in HSUART1" |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 54 | default n |
| 55 | depends on ! ENABLE_BUILTIN_HSUART0 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 56 | select NO_UART_ON_SUPERIO |
| 57 | select DRIVERS_UART_8250MEM_32 |
| 58 | help |
| 59 | The Quark SoC has two HSUART. Choose this option to configure the pads |
| 60 | and enable HSUART1, which can be used for the debug console. |
| 61 | |
| 62 | config TTYS0_BASE |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 63 | hex "HSUART Base Address" |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 64 | default 0xA0019000 |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 65 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 66 | help |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 67 | Memory mapped MMIO of HSUART. |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 68 | |
| 69 | config TTYS0_LCS |
| 70 | int |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 71 | default 3 |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 72 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 73 | |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 74 | # Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12 |
Lee Leahy | 614ef40 | 2016-05-04 12:50:51 -0700 | [diff] [blame] | 75 | # Valid bit, PCI UART in use: 1 << 31 |
| 76 | config UART_PCI_ADDR |
| 77 | hex |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame^] | 78 | default 0x800a1000 if ENABLE_BUILTIN_HSUART0 |
| 79 | default 0x800a5000 if ENABLE_BUILTIN_HSUART1 |
| 80 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 614ef40 | 2016-05-04 12:50:51 -0700 | [diff] [blame] | 81 | |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 82 | ##### |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 83 | # Debug support |
| 84 | # The following options provide debug support for the Quark coreboot |
| 85 | # code. The SD LED is used as a binary marker to determine if a |
| 86 | # specific point in the execution flow has been reached. |
| 87 | ##### |
| 88 | |
| 89 | config ENABLE_DEBUG_LED |
| 90 | bool |
| 91 | default n |
| 92 | help |
| 93 | Enable the use of the SD LED for early debugging before serial output |
| 94 | is available. Setting this LED indicates that control has reached the |
| 95 | desired check point. |
| 96 | |
| 97 | config ENABLE_DEBUG_LED_ESRAM |
| 98 | bool "SD LED indicates ESRAM initialized" |
| 99 | default n |
| 100 | select ENABLE_DEBUG_LED |
| 101 | help |
| 102 | Indicate that ESRAM has been successfully initialized. |
| 103 | |
| 104 | config ENABLE_DEBUG_LED_FINDFSP |
| 105 | bool "SD LED indicates fsp.bin file was found" |
| 106 | default n |
| 107 | select ENABLE_DEBUG_LED |
| 108 | help |
| 109 | Indicate that fsp.bin was found. |
| 110 | |
| 111 | config ENABLE_DEBUG_LED_TEMPRAMINIT |
| 112 | bool "SD LED indicates TempRamInit was successful" |
| 113 | default n |
| 114 | select ENABLE_DEBUG_LED |
| 115 | help |
| 116 | Indicate that TempRamInit was successful. |
| 117 | |
| 118 | ##### |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 119 | # ESRAM layout |
| 120 | # Specify the portion of the ESRAM for coreboot to use as its data area. |
| 121 | ##### |
| 122 | |
| 123 | config DCACHE_RAM_BASE |
| 124 | hex |
| 125 | default 0x80070000 |
| 126 | |
| 127 | config DCACHE_RAM_SIZE |
| 128 | hex |
| 129 | default 0x00008000 |
| 130 | |
| 131 | ##### |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 132 | # Flash layout |
| 133 | # Specify the size of the coreboot file system in the read-only |
| 134 | # (recovery) portion of the flash part. |
| 135 | ##### |
| 136 | |
| 137 | config CBFS_SIZE |
| 138 | hex |
| 139 | default 0x200000 |
| 140 | help |
| 141 | Specify the size of the coreboot file system in the read-only (recovery) |
| 142 | portion of the flash part. On Quark systems the firmware image stores |
| 143 | more than just coreboot, including: |
| 144 | - The chipset microcode (RMU) binary file located at 0xFFF00000 |
| 145 | - Intel Trusted Execution Engine firmware |
| 146 | |
| 147 | ##### |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 148 | # FSP binary |
| 149 | # The following options control the FSP binary file placement in |
| 150 | # the flash image and ESRAM. This file is required by the Quark |
| 151 | # SoC code to boot coreboot and its payload. |
| 152 | ##### |
| 153 | |
| 154 | config ADD_FSP_RAW_BIN |
| 155 | bool "Add the Intel FSP binary to the flash image without relocation" |
| 156 | default n |
| 157 | depends on PLATFORM_USES_FSP1_1 |
| 158 | help |
| 159 | Select this option to add an Intel FSP binary to |
| 160 | the resulting coreboot image. |
| 161 | |
| 162 | Note: Without this binary, coreboot builds relying on the FSP |
| 163 | will not boot |
| 164 | |
| 165 | config FSP_FILE |
| 166 | string "Intel FSP binary path and filename" |
| 167 | default "3rdparty/blobs/soc/intel/quark/fsp.bin" |
| 168 | depends on PLATFORM_USES_FSP1_1 |
| 169 | depends on ADD_FSP_RAW_BIN |
| 170 | help |
| 171 | The path and filename of the Intel FSP binary for this platform. |
| 172 | |
| 173 | config FSP_IMAGE_ID_STRING |
| 174 | string "8 byte platform string identifying the FSP platform" |
| 175 | default "QUK-FSP0" |
| 176 | depends on PLATFORM_USES_FSP1_1 |
| 177 | help |
| 178 | 8 ASCII character byte signature string that will help match the FSP |
| 179 | binary to a supported hardware configuration. |
| 180 | |
| 181 | config FSP_LOC |
| 182 | hex |
| 183 | default 0xfff80000 |
| 184 | depends on PLATFORM_USES_FSP1_1 |
| 185 | help |
| 186 | The location in CBFS that the FSP is located. This must match the |
| 187 | value that is set in the FSP binary. If the FSP needs to be moved, |
| 188 | rebase the FSP with Intel's BCT (tool). |
| 189 | |
| 190 | config FSP_ESRAM_LOC |
| 191 | hex |
| 192 | default 0x80000000 |
| 193 | depends on PLATFORM_USES_FSP1_1 |
| 194 | help |
| 195 | The location in ESRAM where a copy of the FSP binary is placed. |
| 196 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 197 | config RELOCATE_FSP_INTO_DRAM |
| 198 | bool "Relocate FSP into DRAM" |
| 199 | default n |
| 200 | depends on PLATFORM_USES_FSP1_1 |
| 201 | help |
| 202 | Relocate the FSP binary into DRAM before the call to SiliconInit. |
| 203 | |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 204 | ##### |
| 205 | # FSP PDAT binary |
| 206 | # The following options control the FSP platform data binary |
| 207 | # file placement in the flash image. |
| 208 | ##### |
| 209 | |
| 210 | config ADD_FSP_PDAT_FILE |
| 211 | bool "Should the PDAT binary be added to the flash image?" |
| 212 | default n |
| 213 | depends on PLATFORM_USES_FSP1_1 |
| 214 | help |
| 215 | The PDAT file is required for the FSP 1.1 binary |
| 216 | |
| 217 | config FSP_PDAT_FILE |
| 218 | string |
| 219 | default "3rdparty/blobs/soc/intel/quark/pdat.bin" |
| 220 | depends on PLATFORM_USES_FSP1_1 |
| 221 | depends on ADD_FSP_PDAT_FILE |
| 222 | help |
| 223 | The path and filename of the Intel Galileo platform-data-patch (PDAT) |
| 224 | binary. This binary file is generated by the platform-data-patch.py |
| 225 | script released with the Quark BSP and contains the Ethernet address. |
| 226 | |
| 227 | config FSP_PDAT_LOC |
| 228 | hex |
| 229 | default 0xfff10000 |
| 230 | depends on PLATFORM_USES_FSP1_1 |
| 231 | depends on ADD_FSP_PDAT_FILE |
| 232 | help |
| 233 | The location in CBFS that the PDAT is located. It must match the |
| 234 | PCD PcdPlatformDataBaseAddress of Quark SoC FSP. |
| 235 | |
| 236 | ##### |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 237 | # RMU binary |
| 238 | # The following options control the Quark chipset microcode file |
| 239 | # placement in the flash image. This file is required to bring |
| 240 | # the Quark processor out of reset. |
| 241 | ##### |
| 242 | |
| 243 | config ADD_RMU_FILE |
| 244 | bool "Should the RMU binary be added to the flash image?" |
| 245 | default n |
| 246 | help |
| 247 | The RMU file is required to get the chip out of reset. |
| 248 | |
| 249 | config RMU_FILE |
| 250 | string |
| 251 | default "3rdparty/blobs/soc/intel/quark/rmu.bin" |
| 252 | depends on ADD_RMU_FILE |
| 253 | help |
| 254 | The path and filename of the Intel Quark RMU binary. |
| 255 | |
| 256 | config RMU_LOC |
| 257 | hex |
| 258 | default 0xfff00000 |
| 259 | depends on ADD_RMU_FILE |
| 260 | help |
| 261 | The location in CBFS that the RMU is located. It must match the |
| 262 | strap-determined base address. |
| 263 | |
Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 264 | endif # SOC_INTEL_QUARK |