Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lijian Zhao | b269f87 | 2018-07-31 17:23:32 -0700 | [diff] [blame] | 4 | * Copyright (C) 2016-2018 Intel Corporation. |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 16 | #include <device/device.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 17 | #include <device/pci.h> |
| 18 | #include <fsp/api.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 19 | #include <fsp/util.h> |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 20 | #include <intelblocks/acpi.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 21 | #include <intelblocks/cfg.h> |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 22 | #include <intelblocks/itss.h> |
Duncan Laurie | 2410cd9 | 2018-03-26 02:25:07 -0700 | [diff] [blame] | 23 | #include <intelblocks/xdci.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 24 | #include <romstage_handoff.h> |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 25 | #include <soc/intel/common/vbt.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 27 | #include <soc/ramstage.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 28 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 29 | #include "chip.h" |
| 30 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 31 | #if CONFIG(HAVE_ACPI_TABLES) |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 32 | const char *soc_acpi_name(const struct device *dev) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 33 | { |
| 34 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 35 | return "PCI0"; |
| 36 | |
Duncan Laurie | 1e64d23 | 2018-12-01 17:00:23 -0800 | [diff] [blame] | 37 | if (dev->path.type == DEVICE_PATH_USB) { |
| 38 | switch (dev->path.usb.port_type) { |
| 39 | case 0: |
| 40 | /* Root Hub */ |
| 41 | return "RHUB"; |
| 42 | case 2: |
| 43 | /* USB2 ports */ |
| 44 | switch (dev->path.usb.port_id) { |
| 45 | case 0: return "HS01"; |
| 46 | case 1: return "HS02"; |
| 47 | case 2: return "HS03"; |
| 48 | case 3: return "HS04"; |
| 49 | case 4: return "HS05"; |
| 50 | case 5: return "HS06"; |
| 51 | case 6: return "HS07"; |
| 52 | case 7: return "HS08"; |
| 53 | case 8: return "HS09"; |
| 54 | case 9: return "HS10"; |
| 55 | case 10: return "HS11"; |
| 56 | case 11: return "HS12"; |
| 57 | } |
| 58 | break; |
| 59 | case 3: |
| 60 | /* USB3 ports */ |
| 61 | switch (dev->path.usb.port_id) { |
| 62 | case 0: return "SS01"; |
| 63 | case 1: return "SS02"; |
| 64 | case 2: return "SS03"; |
| 65 | case 3: return "SS04"; |
| 66 | case 4: return "SS05"; |
| 67 | case 5: return "SS06"; |
| 68 | } |
| 69 | break; |
| 70 | } |
| 71 | return NULL; |
| 72 | } |
| 73 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 74 | if (dev->path.type != DEVICE_PATH_PCI) |
| 75 | return NULL; |
| 76 | |
| 77 | switch (dev->path.pci.devfn) { |
| 78 | case SA_DEVFN_ROOT: return "MCHC"; |
| 79 | case SA_DEVFN_IGD: return "GFX0"; |
| 80 | case PCH_DEVFN_ISH: return "ISHB"; |
| 81 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 82 | case PCH_DEVFN_USBOTG: return "XDCI"; |
| 83 | case PCH_DEVFN_THERMAL: return "THRM"; |
| 84 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 85 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 86 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 87 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 88 | case PCH_DEVFN_CSE: return "CSE1"; |
| 89 | case PCH_DEVFN_CSE_2: return "CSE2"; |
| 90 | case PCH_DEVFN_CSE_IDER: return "CSED"; |
| 91 | case PCH_DEVFN_CSE_KT: return "CSKT"; |
| 92 | case PCH_DEVFN_CSE_3: return "CSE3"; |
| 93 | case PCH_DEVFN_SATA: return "SATA"; |
| 94 | case PCH_DEVFN_UART2: return "UAR2"; |
| 95 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 96 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 97 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 98 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 99 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 100 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 101 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 102 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 103 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 104 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 105 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 106 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 107 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 108 | case PCH_DEVFN_PCIE12: return "RP12"; |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 109 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 110 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 111 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 112 | case PCH_DEVFN_PCIE16: return "RP16"; |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 113 | case PCH_DEVFN_PCIE17: return "RP17"; |
| 114 | case PCH_DEVFN_PCIE18: return "RP18"; |
| 115 | case PCH_DEVFN_PCIE19: return "RP19"; |
| 116 | case PCH_DEVFN_PCIE20: return "RP20"; |
| 117 | case PCH_DEVFN_PCIE21: return "RP21"; |
| 118 | case PCH_DEVFN_PCIE22: return "RP22"; |
| 119 | case PCH_DEVFN_PCIE23: return "RP23"; |
| 120 | case PCH_DEVFN_PCIE24: return "RP24"; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 121 | case PCH_DEVFN_UART0: return "UAR0"; |
| 122 | case PCH_DEVFN_UART1: return "UAR1"; |
| 123 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 124 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 125 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 126 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 127 | case PCH_DEVFN_SDCARD: return "SDXC"; |
| 128 | case PCH_DEVFN_LPC: return "LPCB"; |
| 129 | case PCH_DEVFN_P2SB: return "P2SB"; |
| 130 | case PCH_DEVFN_PMC: return "PMC_"; |
| 131 | case PCH_DEVFN_HDA: return "HDAS"; |
| 132 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 133 | case PCH_DEVFN_SPI: return "FSPI"; |
| 134 | case PCH_DEVFN_GBE: return "IGBE"; |
| 135 | case PCH_DEVFN_TRACEHUB:return "THUB"; |
| 136 | } |
| 137 | |
| 138 | return NULL; |
| 139 | } |
| 140 | #endif |
| 141 | |
Furquan Shaikh | 86d2afb | 2019-02-05 13:59:47 -0800 | [diff] [blame] | 142 | /* |
| 143 | * TODO(furquan): Get rid of this workaround once FSP is fixed. Currently, FSP-S |
| 144 | * configures GPIOs when it should not and this results in coreboot GPIO |
| 145 | * configuration being overwritten. Until FSP is fixed, maintain the reference |
| 146 | * of GPIO config table from mainboard and use that to re-configure GPIOs after |
| 147 | * FSP-S is done. |
| 148 | */ |
| 149 | void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) |
| 150 | { |
| 151 | static const struct pad_config *g_cfg; |
| 152 | static size_t g_num_pads; |
| 153 | |
| 154 | /* |
| 155 | * If cfg and num_pads are passed in from mainboard, maintain a |
| 156 | * reference to the GPIO table. |
| 157 | */ |
| 158 | if ((cfg == NULL) || (num_pads == 0)) { |
| 159 | cfg = g_cfg; |
| 160 | num_pads = g_num_pads; |
| 161 | } else { |
| 162 | g_cfg = cfg; |
| 163 | g_num_pads = num_pads; |
| 164 | } |
| 165 | |
| 166 | gpio_configure_pads(cfg, num_pads); |
| 167 | } |
| 168 | |
Subrata Banik | 76a8f9e | 2019-05-15 21:23:18 +0530 | [diff] [blame] | 169 | /* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ |
| 170 | static void soc_fill_gpio_pm_configuration(void) |
| 171 | { |
| 172 | uint8_t value[TOTAL_GPIO_COMM]; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 173 | const config_t *config = config_of_soc(); |
Subrata Banik | 76a8f9e | 2019-05-15 21:23:18 +0530 | [diff] [blame] | 174 | |
| 175 | if (config->gpio_override_pm) |
| 176 | memcpy(value, config->gpio_pm, sizeof(uint8_t) * |
| 177 | TOTAL_GPIO_COMM); |
| 178 | else |
| 179 | memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * |
| 180 | TOTAL_GPIO_COMM); |
| 181 | |
| 182 | gpio_pm_configure(value, TOTAL_GPIO_COMM); |
| 183 | } |
| 184 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 185 | void soc_init_pre_device(void *chip_info) |
| 186 | { |
| 187 | /* Perform silicon specific init. */ |
| 188 | fsp_silicon_init(romstage_handoff_is_resume()); |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 189 | |
| 190 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 191 | fsp_display_fvi_version_hob(); |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 192 | |
Furquan Shaikh | 86d2afb | 2019-02-05 13:59:47 -0800 | [diff] [blame] | 193 | /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ |
| 194 | cnl_configure_pads(NULL, 0); |
Subrata Banik | 76a8f9e | 2019-05-15 21:23:18 +0530 | [diff] [blame] | 195 | |
| 196 | soc_fill_gpio_pm_configuration(); |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 197 | } |
| 198 | |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 199 | static void pci_domain_set_resources(struct device *dev) |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 200 | { |
| 201 | assign_resources(dev->link_list); |
| 202 | } |
| 203 | |
| 204 | static struct device_operations pci_domain_ops = { |
| 205 | .read_resources = &pci_domain_read_resources, |
| 206 | .set_resources = &pci_domain_set_resources, |
| 207 | .scan_bus = &pci_domain_scan_bus, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 208 | #if CONFIG(HAVE_ACPI_TABLES) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 209 | .acpi_name = &soc_acpi_name, |
| 210 | #endif |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | static struct device_operations cpu_bus_ops = { |
| 214 | .read_resources = DEVICE_NOOP, |
| 215 | .set_resources = DEVICE_NOOP, |
| 216 | .enable_resources = DEVICE_NOOP, |
| 217 | .init = DEVICE_NOOP, |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 218 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 219 | }; |
| 220 | |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 221 | static void soc_enable(struct device *dev) |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 222 | { |
| 223 | /* Set the operations if it is a special bus type */ |
| 224 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 225 | dev->ops = &pci_domain_ops; |
| 226 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 227 | dev->ops = &cpu_bus_ops; |
| 228 | } |
| 229 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 230 | struct chip_operations soc_intel_cannonlake_ops = { |
| 231 | CHIP_NAME("Intel Cannonlake") |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 232 | .enable_dev = &soc_enable, |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 233 | .init = &soc_init_pre_device, |
| 234 | }; |