commit b269f873b0a0d43911adc907a53bbebadc742b78
author Lijian Zhao <lijian.zhao@intel.com> Tue Jul 31 17:23:32 2018 -0700
committer Patrick Georgi <pgeorgi@google.com> Fri Sep 28 09:53:01 2018 +0000
tree 23e53691cef9dcfd19d63d8128e28638699aae97
parent 80346d04906261b258e1f7ea737a74beac08b11a

soc/intel/cannonlake: Update UPD from device switch

Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.

BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.

Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/chip.c

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 30719ed..34a2fe0 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2016-2017 Intel Corporation.
+ * Copyright (C) 2016-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -208,16 +208,25 @@
 	params->PchLockDownRtcMemoryLock = 0;
 
 	/* SATA */
-	params->SataEnable = config->SataEnable;
-	params->SataMode = config->SataMode;
-	params->SataSalpSupport = config->SataSalpSupport;
-	memcpy(params->SataPortsEnable, config->SataPortsEnable,
+	dev = dev_find_slot(0, PCH_DEVFN_SATA);
+	if (!dev)
+		params->SataEnable = 0;
+	else {
+		params->SataEnable = dev->enabled;
+		params->SataMode = config->SataMode;
+		params->SataSalpSupport = config->SataSalpSupport;
+		memcpy(params->SataPortsEnable, config->SataPortsEnable,
 			sizeof(params->SataPortsEnable));
-	memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
+		memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
 			sizeof(params->SataPortsDevSlp));
+	}
 
 	/* Lan */
-	params->PchLanEnable = config->PchLanEnable;
+	dev = dev_find_slot(0, PCH_DEVFN_GBE);
+	if (!dev)
+		params->PchLanEnable = 0;
+	else
+		params->PchLanEnable = dev->enabled;
 
 	/* Audio */
 	params->PchHdaDspEnable = config->PchHdaDspEnable;
@@ -237,18 +246,13 @@
 
 	/* USB */
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
-		params->PortUsb20Enable[i] =
-			config->usb2_ports[i].enable;
-		params->Usb2OverCurrentPin[i] =
-			config->usb2_ports[i].ocpin;
-		params->Usb2AfePetxiset[i] =
-			config->usb2_ports[i].pre_emp_bias;
-		params->Usb2AfeTxiset[i] =
-			config->usb2_ports[i].tx_bias;
+		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+		params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+		params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
 		params->Usb2AfePredeemp[i] =
 			config->usb2_ports[i].tx_emp_enable;
-		params->Usb2AfePehalfbit[i] =
-			config->usb2_ports[i].pre_emp_bit;
+		params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 	}
 
 	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
@@ -283,16 +287,32 @@
 	       sizeof(config->PcieClkSrcClkReq));
 
 	/* eMMC and SD */
-	params->ScsEmmcEnabled = config->ScsEmmcEnabled;
-	params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
-	params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
-	if (config->EmmcHs400DllNeed == 1) {
-		params->PchScsEmmcHs400RxStrobeDll1 =
-			config->EmmcHs400RxStrobeDll1;
-		params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;
+	dev = dev_find_slot(0, PCH_DEVFN_EMMC);
+	if (!dev)
+		params->ScsEmmcEnabled = 0;
+	else {
+		params->ScsEmmcEnabled = dev->enabled;
+		params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+		params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
+		if (config->EmmcHs400DllNeed == 1) {
+			params->PchScsEmmcHs400RxStrobeDll1 =
+				config->EmmcHs400RxStrobeDll1;
+			params->PchScsEmmcHs400TxDataDll =
+				config->EmmcHs400TxDataDll;
+		}
 	}
-	params->ScsSdCardEnabled = config->ScsSdCardEnabled;
-	params->ScsUfsEnabled = config->ScsUfsEnabled;
+
+	dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+	if (!dev)
+		params->ScsSdCardEnabled = 0;
+	else
+		params->ScsSdCardEnabled = dev->enabled;
+
+	dev = dev_find_slot(0, PCH_DEVFN_UFS);
+	if (!dev)
+		params->ScsUfsEnabled = 0;
+	else
+		params->ScsUfsEnabled = dev->enabled;
 
 	params->Heci3Enabled = config->Heci3Enabled;
 	params->Device4Enable = config->Device4Enable;