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review.coreboot.org / coreboot / 6e732d34a0c1b87803925065b66076599c1e5642 / . / src / southbridge / intel / i82801ix / acpi / ich9.asl
blob: 3455acf981780e6c020791dc5e49d4df48b114d9 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]2
3/* Intel 82801Ix support */
4
5Scope(\)
6{
7 // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
8
9 OperationRegion(IO_T, SystemIO, 0x800, 0x10)
10 Field(IO_T, ByteAcc, NoLock, Preserve)
11 {
12 Offset(0x8),
13 TRP0, 8 // IO-Trap at 0x808
14 }
15
16 // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
17 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
18 Field(PMIO, ByteAcc, NoLock, Preserve)
19 {
20 Offset(0x11),
21 THRO, 1, // force thermal throttling
22 Offset(0x42), // General Purpose Control
23 , 1, // skip 1 bit
24 GPEC, 1, // TCO status
25 Offset(0x64),
26 , 9, // skip 9 more bits
27 SCIS, 1 // TCO DMI status
28 }
29
30 // FIXME: purposes of the GPIOs (comments) are probably wrong
31 // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
32 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
33 Field(GPIO, ByteAcc, NoLock, Preserve)
34 {
Elyes HAOUAS48a6c012020-07-08 09:22:13 +0200[diff] [blame]35 GU00, 8, // GPIO Use Select
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]36 GU01, 8,
37 GU02, 8,
38 GU03, 8,
39 Offset(0x04), // GPIO IO Select
40 GIO0, 8,
41 GIO1, 8,
42 GIO2, 8,
43 GIO3, 8,
44 Offset(0x0c), // GPIO Level
45 GP00, 1,
46 GP01, 1,
47 GP02, 1,
48 GP03, 1,
49 GP04, 1,
50 GP05, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]51 GP06, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]52 GP07, 1,
53 GP08, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]54 GP09, 1,
55 GP10, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]56 GP11, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]57 GP12, 1,
58 GP13, 1,
59 GP14, 1,
60 GP15, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]61 GP16, 1,
62 GP17, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]63 GP18, 1,
64 GP19, 1,
65 GP20, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]66 GP21, 1,
67 GP22, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]68 GP23, 1,
69 GP24, 1,
70 GP25, 1,
71 GP26, 1,
72 GP27, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]73 GP28, 1,
74 GP29, 1,
75 GP30, 1,
76 GP31, 1,
77 Offset(0x18), // GPIO Blink
78 GB00, 8,
79 GB01, 8,
80 GB02, 8,
81 GB03, 8,
82 Offset(0x2c), // GPIO Invert
83 GIV0, 8,
84 GIV1, 8,
85 GIV2, 8,
86 GIV3, 8,
87 Offset(0x30), // GPIO Use Select 2
88 GU04, 8,
89 GU05, 8,
90 GU06, 8,
91 GU07, 8,
92 Offset(0x34), // GPIO IO Select 2
93 GIO4, 8,
94 GIO5, 8,
95 GIO6, 8,
96 GIO7, 8,
97 Offset(0x38), // GPIO Level 2
98 GP32, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]99 GP33, 1,
100 GP34, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]101 GP35, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]102 GP36, 1,
103 GP37, 1,
104 GP38, 1,
105 GP39, 1,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]106 GL05, 8,
107 GL06, 8,
108 GL07, 8
109 }
110
111
112 // ICH9 Root Complex Register Block. Memory Mapped through RCBA)
Angel Pons6e732d32021-01-28 13:56:18 +0100[diff] [blame^]113 OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]114 Field(RCRB, DWordAcc, Lock, Preserve)
115 {
116 Offset(0x0000), // Backbone
117 Offset(0x1000), // Chipset
118 Offset(0x3000), // Legacy Configuration Registers
119 Offset(0x3404), // High Performance Timer Configuration
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200[diff] [blame]120 HPAS, 2, // Address Select
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]121 , 5,
122 HPTE, 1, // Address Enable
123 Offset(0x3418), // FD (Function Disable)
124 , 2, // Reserved
125 SA1D, 1, // SATA disable
126 SMBD, 1, // SMBUS disable
127 HDAD, 1, // Azalia disable
128 , 2, // Reserved
129 US6D, 1, // UHCI #6 disable
130 US1D, 1, // UHCI #1 disable
131 US2D, 1, // UHCI #2 disable
132 US3D, 1, // UHCI #3 disable
133 US4D, 1, // UHCI #4 disable
134 US5D, 1, // UHCI #5 disable
135 EH2D, 1, // EHCI disable
136 LPBD, 1, // LPC bridge disable
137 EH1D, 1, // EHCI disable
138 Offset(0x341a), // FD Root Ports
139 RP1D, 1, // Root Port 1 disable
140 RP2D, 1, // Root Port 2 disable
141 RP3D, 1, // Root Port 3 disable
142 RP4D, 1, // Root Port 4 disable
143 RP5D, 1, // Root Port 5 disable
144 RP6D, 1, // Root Port 6 disable
145 , 2, // Reserved
146 THRD, 1, // Thermal Throttle disable
147 SA2D, 1, // SATA disable
148 }
149
150}
151
152// 0:1b.0 High Definition Audio (Azalia)
Angel Ponsb6427b02020-07-07 01:29:40 +0200[diff] [blame]153#include <southbridge/intel/common/acpi/audio_ich.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]154
155// PCI Express Ports
Arthur Heymansdff185a2018-12-30 12:59:39 +0100[diff] [blame]156#include <southbridge/intel/common/acpi/pcie.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]157
158// USB
159#include "usb.asl"
160
161// PCI Bridge
162#include "pci.asl"
163
164// LPC Bridge
165#include "lpc.asl"
166
167// SATA
168#include "sata.asl"
169
170// SMBus
Elyes HAOUAS085ab5a2019-10-31 10:12:02 +0100[diff] [blame]171#include <southbridge/intel/common/acpi/smbus.asl>
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]172
173Method (_OSC, 4)
174{
175 /* Check for proper GUID */
176 If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
177 {
178 /* Let OS control everything */
179 Return (Arg3)
180 }
181 Else
182 {
183 /* Unrecognized UUID */
184 CreateDWordField (Arg3, 0, CDW1)
185 Or (CDW1, 4, CDW1)
186 Return (Arg3)
187 }
188}