Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 2 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 3 | #include <device/pci_ops.h> |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 4 | #include <device/smbus_host.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 5 | #include <cbmem.h> |
Elyes HAOUAS | b559b3c | 2019-04-28 17:52:10 +0200 | [diff] [blame] | 6 | #include <cf9_reset.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 7 | #include <console/console.h> |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 8 | #include <arch/cpu.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 9 | #include <spd.h> |
| 10 | #include <string.h> |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 11 | #include <device/dram/ddr2.h> |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 12 | #include <device/dram/ddr3.h> |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 13 | #include <mrc_cache.h> |
Elyes HAOUAS | f5a57a8 | 2019-01-08 22:15:53 +0100 | [diff] [blame] | 14 | #include <timestamp.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 15 | #include <types.h> |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 16 | |
Angel Pons | 41e66ac | 2020-09-15 13:17:23 +0200 | [diff] [blame] | 17 | #include "raminit.h" |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 18 | #include "x4x.h" |
| 19 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 20 | #define MRC_CACHE_VERSION 0 |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 21 | |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 22 | static u16 ddr2_get_crc(u8 device, u8 len) |
| 23 | { |
| 24 | u8 raw_spd[128] = {}; |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 25 | i2c_eeprom_read(device, 64, 9, &raw_spd[64]); |
| 26 | i2c_eeprom_read(device, 93, 6, &raw_spd[93]); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 27 | return spd_ddr2_calc_unique_crc(raw_spd, len); |
| 28 | } |
| 29 | |
| 30 | static u16 ddr3_get_crc(u8 device, u8 len) |
| 31 | { |
| 32 | u8 raw_spd[256] = {}; |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 33 | i2c_eeprom_read(device, 117, 11, &raw_spd[117]); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 34 | return spd_ddr3_calc_unique_crc(raw_spd, len); |
| 35 | } |
| 36 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 37 | static enum cb_err verify_spds(const u8 *spd_map, const struct sysinfo *ctrl_cached) |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 38 | { |
| 39 | int i; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 40 | u16 crc; |
| 41 | |
| 42 | for (i = 0; i < TOTAL_DIMMS; i++) { |
| 43 | if (!(spd_map[i])) |
| 44 | continue; |
| 45 | int len = smbus_read_byte(spd_map[i], 0); |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 46 | if (len < 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED) |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 47 | continue; |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 48 | if (len > 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED) |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 49 | return CB_ERR; |
| 50 | |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 51 | if (ctrl_cached->spd_type == DDR2) |
| 52 | crc = ddr2_get_crc(spd_map[i], len); |
| 53 | else |
| 54 | crc = ddr3_get_crc(spd_map[i], len); |
| 55 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 56 | if (crc != ctrl_cached->dimms[i].spd_crc) |
| 57 | return CB_ERR; |
| 58 | } |
| 59 | return CB_SUCCESS; |
| 60 | } |
| 61 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 62 | struct abs_timings { |
| 63 | u32 min_tclk; |
| 64 | u32 min_tRAS; |
| 65 | u32 min_tRP; |
| 66 | u32 min_tRCD; |
| 67 | u32 min_tWR; |
| 68 | u32 min_tRFC; |
| 69 | u32 min_tWTR; |
| 70 | u32 min_tRRD; |
| 71 | u32 min_tRTP; |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 72 | u32 min_tAA; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 73 | u32 min_tCLK_cas[8]; |
| 74 | u32 cas_supported; |
| 75 | }; |
| 76 | |
| 77 | #define CTRL_MIN_TCLK_DDR2 TCK_400MHZ |
| 78 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 79 | static void select_cas_dramfreq_ddr2(struct sysinfo *s, const struct abs_timings *saved_timings) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 80 | { |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 81 | u8 try_cas; |
| 82 | /* Currently only these CAS are supported */ |
| 83 | u8 cas_mask = SPD_CAS_LATENCY_DDR2_5 | SPD_CAS_LATENCY_DDR2_6; |
Arthur Heymans | cfa2eaa | 2017-03-20 16:32:07 +0100 | [diff] [blame] | 84 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 85 | cas_mask &= saved_timings->cas_supported; |
| 86 | try_cas = spd_get_msbs(cas_mask); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 87 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 88 | while (cas_mask & (1 << try_cas) && try_cas > 0) { |
| 89 | s->selected_timings.CAS = try_cas; |
| 90 | s->selected_timings.tclk = saved_timings->min_tCLK_cas[try_cas]; |
| 91 | if (s->selected_timings.tclk >= CTRL_MIN_TCLK_DDR2 && |
| 92 | saved_timings->min_tCLK_cas[try_cas] != |
| 93 | saved_timings->min_tCLK_cas[try_cas - 1]) |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 94 | break; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 95 | try_cas--; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 96 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 97 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 98 | if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0)) |
| 99 | die("Could not find common memory frequency and CAS\n"); |
| 100 | |
| 101 | switch (s->selected_timings.tclk) { |
| 102 | case TCK_200MHZ: |
| 103 | case TCK_266MHZ: |
| 104 | /* FIXME: this works on vendor BIOS */ |
| 105 | die("Selected dram frequency not supported\n"); |
| 106 | case TCK_333MHZ: |
| 107 | s->selected_timings.mem_clk = MEM_CLOCK_667MHz; |
| 108 | break; |
| 109 | case TCK_400MHZ: |
| 110 | s->selected_timings.mem_clk = MEM_CLOCK_800MHz; |
| 111 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 112 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | static void mchinfo_ddr2(struct sysinfo *s) |
| 116 | { |
| 117 | const u32 eax = cpuid_ext(0x04, 0).eax; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 118 | printk(BIOS_WARNING, "%d CPU cores\n", ((eax >> 26) & 0x3f) + 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 119 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 120 | u32 capid = pci_read_config16(HOST_BRIDGE, 0xe8); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 121 | if (!(capid & (1<<(79-64)))) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 122 | printk(BIOS_WARNING, "iTPM enabled\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 123 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 124 | capid = pci_read_config32(HOST_BRIDGE, 0xe4); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 125 | if (!(capid & (1<<(57-32)))) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 126 | printk(BIOS_WARNING, "ME enabled\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 127 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 128 | if (!(capid & (1<<(56-32)))) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 129 | printk(BIOS_WARNING, "AMT enabled\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 130 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 131 | if (!(capid & (1<<(48-32)))) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 132 | printk(BIOS_WARNING, "VT-d enabled\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 133 | } |
| 134 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 135 | static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, |
| 136 | struct abs_timings *saved_timings, struct sysinfo *s) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 137 | { |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 138 | struct dimm_attr_ddr2_st decoded_dimm; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 139 | int i; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 140 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 141 | if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) { |
| 142 | printk(BIOS_DEBUG, "Problems decoding SPD\n"); |
| 143 | return CB_ERR; |
| 144 | } |
Damien Zammit | 7c2e539 | 2016-07-24 03:28:42 +1000 | [diff] [blame] | 145 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 146 | if (CONFIG(DEBUG_RAM_SETUP)) |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 147 | dram_print_spd_ddr2(&decoded_dimm); |
| 148 | |
| 149 | if (!(decoded_dimm.width & (0x08 | 0x10))) { |
| 150 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 151 | printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n", |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 152 | dimm_idx, s->dimms[dimm_idx].width); |
| 153 | return CB_ERR; |
| 154 | } |
| 155 | s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1; |
| 156 | /* |
| 157 | * This boils down to: |
| 158 | * "Except for the x16 configuration, all DDR2 devices have a |
| 159 | * 1KB page size. For the x16 configuration, the page size is 2KB |
| 160 | * for all densities except the 256Mb device, which has a 1KB page |
| 161 | * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' |
Arthur Heymans | d4e5762 | 2017-12-25 17:01:33 +0100 | [diff] [blame] | 162 | * The formula is pagesize in KiB = width * 2^col_bits / 8. |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 163 | */ |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 164 | s->dimms[dimm_idx].page_size = decoded_dimm.width * (1 << decoded_dimm.col_bits) / 8; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 165 | |
| 166 | switch (decoded_dimm.banks) { |
| 167 | case 4: |
| 168 | s->dimms[dimm_idx].n_banks = N_BANKS_4; |
| 169 | break; |
| 170 | case 8: |
| 171 | s->dimms[dimm_idx].n_banks = N_BANKS_8; |
| 172 | break; |
| 173 | default: |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 174 | printk(BIOS_ERR, "DIMM%d Unsupported #banks: x%d. Disabling dimm\n", |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 175 | dimm_idx, decoded_dimm.banks); |
| 176 | return CB_ERR; |
| 177 | } |
| 178 | |
| 179 | s->dimms[dimm_idx].ranks = decoded_dimm.ranks; |
| 180 | s->dimms[dimm_idx].rows = decoded_dimm.row_bits; |
| 181 | s->dimms[dimm_idx].cols = decoded_dimm.col_bits; |
| 182 | |
| 183 | saved_timings->cas_supported &= decoded_dimm.cas_supported; |
| 184 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 185 | saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); |
| 186 | saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP); |
| 187 | saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); |
| 188 | saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR); |
| 189 | saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); |
| 190 | saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); |
| 191 | saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); |
| 192 | saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 193 | for (i = 0; i < 8; i++) { |
| 194 | if (!(saved_timings->cas_supported & (1 << i))) |
| 195 | saved_timings->min_tCLK_cas[i] = 0; |
| 196 | else |
| 197 | saved_timings->min_tCLK_cas[i] = |
| 198 | MAX(saved_timings->min_tCLK_cas[i], |
| 199 | decoded_dimm.cycle_time[i]); |
| 200 | } |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 201 | |
| 202 | s->dimms[dimm_idx].spd_crc = spd_ddr2_calc_unique_crc(raw_spd, |
| 203 | spd_decode_spd_size_ddr2(raw_spd[0])); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 204 | return CB_SUCCESS; |
| 205 | } |
| 206 | |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 207 | static void normalize_tCLK(u32 *tCLK) |
| 208 | { |
| 209 | if (*tCLK <= TCK_666MHZ) |
| 210 | *tCLK = TCK_666MHZ; |
| 211 | else if (*tCLK <= TCK_533MHZ) |
| 212 | *tCLK = TCK_533MHZ; |
| 213 | else if (*tCLK <= TCK_400MHZ) |
| 214 | *tCLK = TCK_400MHZ; |
| 215 | else |
| 216 | *tCLK = 0; |
| 217 | } |
| 218 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 219 | static void select_cas_dramfreq_ddr3(struct sysinfo *s, struct abs_timings *saved_timings) |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 220 | { |
| 221 | /* |
| 222 | * various constraints must be fulfilled: |
| 223 | * CAS * tCK < 20ns == 160MTB |
| 224 | * tCK_max >= tCK >= tCK_min |
| 225 | * CAS >= roundup(tAA_min/tCK) |
| 226 | * CAS supported |
| 227 | * AND BTW: Clock(MT) = 2000 / tCK(ns) - intel uses MTs but calls them MHz |
| 228 | */ |
| 229 | |
| 230 | u32 min_tCLK; |
| 231 | u8 try_CAS; |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 232 | u16 capid = (pci_read_config16(HOST_BRIDGE, 0xea) >> 4) & 0x3f; |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 233 | |
| 234 | switch (s->max_fsb) { |
| 235 | default: |
| 236 | case FSB_CLOCK_800MHz: |
| 237 | min_tCLK = TCK_400MHZ; |
| 238 | break; |
| 239 | case FSB_CLOCK_1066MHz: |
| 240 | min_tCLK = TCK_533MHZ; |
| 241 | break; |
| 242 | case FSB_CLOCK_1333MHz: |
| 243 | min_tCLK = TCK_666MHZ; |
| 244 | break; |
| 245 | } |
| 246 | |
| 247 | switch (capid >> 3) { |
| 248 | default: /* Should not happen */ |
| 249 | min_tCLK = TCK_400MHZ; |
| 250 | break; |
| 251 | case 1: |
| 252 | min_tCLK = MAX(min_tCLK, TCK_400MHZ); |
| 253 | break; |
| 254 | case 2: |
| 255 | min_tCLK = MAX(min_tCLK, TCK_533MHZ); |
| 256 | break; |
| 257 | case 3: /* Only on P45 */ |
Arthur Heymans | b1ba662 | 2018-10-14 13:22:16 +0200 | [diff] [blame] | 258 | case 0: |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 259 | min_tCLK = MAX(min_tCLK, TCK_666MHZ); |
| 260 | break; |
| 261 | } |
| 262 | |
| 263 | min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); |
| 264 | if (min_tCLK == 0) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 265 | printk(BIOS_ERR, |
Angel Pons | e821914 | 2021-03-26 23:27:22 +0100 | [diff] [blame] | 266 | "DRAM frequency is under lowest supported frequency (400 MHz).\n" |
| 267 | "Increasing to 400 MHz as last resort.\n"); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 268 | min_tCLK = TCK_400MHZ; |
| 269 | } |
| 270 | |
| 271 | while (1) { |
| 272 | normalize_tCLK(&min_tCLK); |
| 273 | if (min_tCLK == 0) |
| 274 | die("Couldn't find compatible clock / CAS settings.\n"); |
| 275 | try_CAS = DIV_ROUND_UP(saved_timings->min_tAA, min_tCLK); |
| 276 | printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", try_CAS, min_tCLK); |
| 277 | for (; try_CAS <= DDR3_MAX_CAS; try_CAS++) { |
| 278 | /* |
| 279 | * cas_supported is encoded like the SPD which starts |
| 280 | * at CAS=4. |
| 281 | */ |
| 282 | if ((saved_timings->cas_supported << 4) & (1 << try_CAS)) |
| 283 | break; |
| 284 | } |
| 285 | if ((try_CAS <= DDR3_MAX_CAS) && (try_CAS * min_tCLK < 20 * 256)) { |
| 286 | /* Found good CAS. */ |
| 287 | printk(BIOS_SPEW, "Found compatible tCLK / CAS pair: %u / %u.\n", |
| 288 | min_tCLK, try_CAS); |
| 289 | break; |
| 290 | } |
| 291 | /* |
| 292 | * If no valid tCLK / CAS pair could be found for a tCLK |
| 293 | * increase it after which it gets normalised. This means |
| 294 | * that a lower frequency gets tried. |
| 295 | */ |
| 296 | min_tCLK++; |
| 297 | } |
| 298 | |
| 299 | s->selected_timings.tclk = min_tCLK; |
| 300 | s->selected_timings.CAS = try_CAS; |
| 301 | |
| 302 | switch (s->selected_timings.tclk) { |
| 303 | case TCK_400MHZ: |
| 304 | s->selected_timings.mem_clk = MEM_CLOCK_800MHz; |
| 305 | break; |
| 306 | case TCK_533MHZ: |
| 307 | s->selected_timings.mem_clk = MEM_CLOCK_1066MHz; |
| 308 | break; |
| 309 | case TCK_666MHZ: |
| 310 | s->selected_timings.mem_clk = MEM_CLOCK_1333MHz; |
| 311 | break; |
| 312 | } |
| 313 | } |
| 314 | |
Arthur Heymans | 5a9dbde | 2018-05-26 15:05:09 +0200 | [diff] [blame] | 315 | /* With DDR3 and 533MHz mem clock and an enabled internal gfx device the display |
| 316 | is not usable in non stacked mode, so select stacked mode accordingly */ |
| 317 | static void workaround_stacked_mode(struct sysinfo *s) |
| 318 | { |
| 319 | u32 deven; |
| 320 | /* Only a problem on DDR3 */ |
| 321 | if (s->spd_type == DDR2) |
| 322 | return; |
| 323 | /* Does not matter if only one channel is populated */ |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 324 | if (!CHANNEL_IS_POPULATED(s->dimms, 0) || !CHANNEL_IS_POPULATED(s->dimms, 1)) |
Arthur Heymans | 5a9dbde | 2018-05-26 15:05:09 +0200 | [diff] [blame] | 325 | return; |
| 326 | if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz) |
| 327 | return; |
| 328 | /* IGD0EN gets disabled if not present before this code runs */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 329 | deven = pci_read_config32(HOST_BRIDGE, D0F0_DEVEN); |
Arthur Heymans | 5a9dbde | 2018-05-26 15:05:09 +0200 | [diff] [blame] | 330 | if (deven & IGD0EN) |
| 331 | s->stacked_mode = 1; |
| 332 | } |
| 333 | |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 334 | static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, |
| 335 | struct abs_timings *saved_timings, struct sysinfo *s) |
| 336 | { |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 337 | struct dimm_attr_ddr3_st decoded_dimm; |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 338 | |
| 339 | if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK) |
| 340 | return CB_ERR; |
| 341 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 342 | if (CONFIG(DEBUG_RAM_SETUP)) |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 343 | dram_print_spd_ddr3(&decoded_dimm); |
| 344 | |
| 345 | /* x4 DIMMs are not supported (true for both ddr2 and ddr3) */ |
| 346 | if (!(decoded_dimm.width & (0x8 | 0x10))) { |
| 347 | printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n", |
| 348 | dimm_idx, s->dimms[dimm_idx].width); |
| 349 | return CB_ERR; |
| 350 | } |
| 351 | s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1; |
| 352 | /* |
| 353 | * This boils down to: |
| 354 | * "Except for the x16 configuration, all DDR3 devices have a |
| 355 | * 1KB page size. For the x16 configuration, the page size is 2KB |
| 356 | * for all densities except the 256Mb device, which has a 1KB page size." |
| 357 | * Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' |
| 358 | */ |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 359 | s->dimms[dimm_idx].page_size = decoded_dimm.width * (1 << decoded_dimm.col_bits) / 8; |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 360 | |
| 361 | s->dimms[dimm_idx].n_banks = N_BANKS_8; /* Always 8 banks on ddr3?? */ |
| 362 | |
| 363 | s->dimms[dimm_idx].ranks = decoded_dimm.ranks; |
| 364 | s->dimms[dimm_idx].rows = decoded_dimm.row_bits; |
| 365 | s->dimms[dimm_idx].cols = decoded_dimm.col_bits; |
| 366 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 367 | saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); |
| 368 | saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP); |
| 369 | saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); |
| 370 | saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR); |
| 371 | saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); |
| 372 | saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); |
| 373 | saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); |
| 374 | saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); |
| 375 | saved_timings->min_tAA = MAX(saved_timings->min_tAA, decoded_dimm.tAA); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 376 | saved_timings->cas_supported &= decoded_dimm.cas_supported; |
| 377 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 378 | s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd, raw_spd[0]); |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 379 | |
| 380 | s->dimms[dimm_idx].mirrored = decoded_dimm.flags.pins_mirrored; |
| 381 | |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 382 | return CB_SUCCESS; |
| 383 | } |
| 384 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 385 | static void select_discrete_timings(struct sysinfo *s, const struct abs_timings *timings) |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 386 | { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 387 | s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS, s->selected_timings.tclk); |
| 388 | s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP, s->selected_timings.tclk); |
| 389 | s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD, s->selected_timings.tclk); |
| 390 | s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR, s->selected_timings.tclk); |
| 391 | s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC, s->selected_timings.tclk); |
| 392 | s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR, s->selected_timings.tclk); |
| 393 | s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD, s->selected_timings.tclk); |
| 394 | s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP, s->selected_timings.tclk); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 395 | } |
| 396 | static void print_selected_timings(struct sysinfo *s) |
| 397 | { |
| 398 | printk(BIOS_DEBUG, "Selected timings:\n"); |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 399 | printk(BIOS_DEBUG, "\tFSB: %dMHz\n", fsb_to_mhz(s->selected_timings.fsb_clk)); |
| 400 | printk(BIOS_DEBUG, "\tDDR: %dMHz\n", ddr_to_mhz(s->selected_timings.mem_clk)); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 401 | |
| 402 | printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS); |
| 403 | printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS); |
| 404 | printk(BIOS_DEBUG, "\ttRP: %d\n", s->selected_timings.tRP); |
| 405 | printk(BIOS_DEBUG, "\ttRCD: %d\n", s->selected_timings.tRCD); |
| 406 | printk(BIOS_DEBUG, "\ttWR: %d\n", s->selected_timings.tWR); |
| 407 | printk(BIOS_DEBUG, "\ttRFC: %d\n", s->selected_timings.tRFC); |
| 408 | printk(BIOS_DEBUG, "\ttWTR: %d\n", s->selected_timings.tWTR); |
| 409 | printk(BIOS_DEBUG, "\ttRRD: %d\n", s->selected_timings.tRRD); |
| 410 | printk(BIOS_DEBUG, "\ttRTP: %d\n", s->selected_timings.tRTP); |
| 411 | } |
| 412 | |
| 413 | static void find_fsb_speed(struct sysinfo *s) |
| 414 | { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 415 | switch ((mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 416 | case 0x0: |
| 417 | s->max_fsb = FSB_CLOCK_1066MHz; |
| 418 | break; |
| 419 | case 0x2: |
| 420 | s->max_fsb = FSB_CLOCK_800MHz; |
| 421 | break; |
| 422 | case 0x4: |
| 423 | s->max_fsb = FSB_CLOCK_1333MHz; |
| 424 | break; |
| 425 | default: |
| 426 | s->max_fsb = FSB_CLOCK_800MHz; |
| 427 | printk(BIOS_WARNING, "Can't detect FSB, setting 800MHz\n"); |
| 428 | break; |
| 429 | } |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 430 | s->selected_timings.fsb_clk = s->max_fsb; |
| 431 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 432 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 433 | static void decode_spd_select_timings(struct sysinfo *s) |
| 434 | { |
| 435 | unsigned int device; |
| 436 | u8 dram_type_mask = (1 << DDR2) | (1 << DDR3); |
| 437 | u8 dimm_mask = 0; |
| 438 | u8 raw_spd[256]; |
| 439 | int i, j; |
| 440 | struct abs_timings saved_timings; |
| 441 | memset(&saved_timings, 0, sizeof(saved_timings)); |
| 442 | saved_timings.cas_supported = UINT32_MAX; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 443 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 444 | FOR_EACH_DIMM(i) { |
| 445 | s->dimms[i].card_type = RAW_CARD_POPULATED; |
| 446 | device = s->spd_map[i]; |
| 447 | if (!device) { |
| 448 | s->dimms[i].card_type = RAW_CARD_UNPOPULATED; |
| 449 | continue; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 450 | } |
Kyösti Mälkki | bd65985 | 2020-01-05 20:00:18 +0200 | [diff] [blame] | 451 | switch (smbus_read_byte(s->spd_map[i], SPD_MEMORY_TYPE)) { |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 452 | case DDR2SPD: |
| 453 | dram_type_mask &= 1 << DDR2; |
| 454 | s->spd_type = DDR2; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 455 | break; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 456 | case DDR3SPD: |
| 457 | dram_type_mask &= 1 << DDR3; |
| 458 | s->spd_type = DDR3; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 459 | break; |
| 460 | default: |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 461 | s->dimms[i].card_type = RAW_CARD_UNPOPULATED; |
| 462 | continue; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 463 | } |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 464 | if (!dram_type_mask) |
| 465 | die("Mixing up dimm types is not supported!\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 466 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 467 | printk(BIOS_DEBUG, "Decoding dimm %d\n", i); |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 468 | if (i2c_eeprom_read(device, 0, 128, raw_spd) != 128) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 469 | printk(BIOS_DEBUG, |
| 470 | "i2c block operation failed, trying smbus byte operation.\n"); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 471 | for (j = 0; j < 128; j++) |
Kyösti Mälkki | bd65985 | 2020-01-05 20:00:18 +0200 | [diff] [blame] | 472 | raw_spd[j] = smbus_read_byte(device, j); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 473 | } |
| 474 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 475 | if (s->spd_type == DDR2){ |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 476 | if (ddr2_save_dimminfo(i, raw_spd, &saved_timings, s)) { |
| 477 | printk(BIOS_WARNING, |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 478 | "Encountered problems with SPD, skipping this DIMM.\n"); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 479 | s->dimms[i].card_type = RAW_CARD_UNPOPULATED; |
| 480 | continue; |
| 481 | } |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 482 | } else { /* DDR3 */ |
| 483 | if (ddr3_save_dimminfo(i, raw_spd, &saved_timings, s)) { |
| 484 | printk(BIOS_WARNING, |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 485 | "Encountered problems with SPD, skipping this DIMM.\n"); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 486 | /* something in decoded SPD was unsupported */ |
| 487 | s->dimms[i].card_type = RAW_CARD_UNPOPULATED; |
| 488 | continue; |
| 489 | } |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 490 | } |
| 491 | dimm_mask |= (1 << i); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 492 | } |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 493 | if (!dimm_mask) |
| 494 | die("No memory installed.\n"); |
| 495 | |
| 496 | if (s->spd_type == DDR2) |
| 497 | select_cas_dramfreq_ddr2(s, &saved_timings); |
Arthur Heymans | 1848ba3 | 2017-04-11 17:09:31 +0200 | [diff] [blame] | 498 | else |
| 499 | select_cas_dramfreq_ddr3(s, &saved_timings); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 500 | select_discrete_timings(s, &saved_timings); |
Arthur Heymans | 5a9dbde | 2018-05-26 15:05:09 +0200 | [diff] [blame] | 501 | workaround_stacked_mode(s); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | static void find_dimm_config(struct sysinfo *s) |
| 505 | { |
| 506 | int chan, i; |
| 507 | |
| 508 | FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) { |
| 509 | FOR_EACH_POPULATED_DIMM_IN_CHANNEL(s->dimms, chan, i) { |
| 510 | int dimm_config; |
| 511 | if (s->dimms[i].ranks == 1) { |
| 512 | if (s->dimms[i].width == 0) /* x8 */ |
| 513 | dimm_config = 1; |
| 514 | else /* x16 */ |
| 515 | dimm_config = 3; |
| 516 | } else { |
| 517 | if (s->dimms[i].width == 0) /* x8 */ |
| 518 | dimm_config = 2; |
| 519 | else |
| 520 | die("Dual-rank x16 not supported\n"); |
| 521 | } |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 522 | s->dimm_config[chan] |= dimm_config << (i % DIMMS_PER_CHANNEL) * 2; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 523 | } |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 524 | printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 525 | } |
| 526 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 527 | } |
| 528 | |
Arthur Heymans | bb5e77c | 2016-11-30 20:37:29 +0100 | [diff] [blame] | 529 | static void checkreset_ddr2(int boot_path) |
| 530 | { |
| 531 | u8 pmcon2; |
| 532 | u32 pmsts; |
| 533 | |
| 534 | if (boot_path >= 1) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 535 | pmsts = mchbar_read32(PMSTS_MCHBAR); |
Arthur Heymans | bb5e77c | 2016-11-30 20:37:29 +0100 | [diff] [blame] | 536 | if (!(pmsts & 1)) |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 537 | printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n"); |
Arthur Heymans | bb5e77c | 2016-11-30 20:37:29 +0100 | [diff] [blame] | 538 | if (!(pmsts & 2)) |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 539 | printk(BIOS_DEBUG, "Channel 1 possibly not in self refresh\n"); |
Arthur Heymans | bb5e77c | 2016-11-30 20:37:29 +0100 | [diff] [blame] | 540 | } |
| 541 | |
| 542 | pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
| 543 | |
| 544 | if (pmcon2 & 0x80) { |
| 545 | pmcon2 &= ~0x80; |
| 546 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); |
| 547 | |
| 548 | /* do magic 0xf0 thing. */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 549 | pci_and_config8(HOST_BRIDGE, 0xf0, ~(1 << 2)); |
Angel Pons | 4a9569a | 2020-06-08 01:39:25 +0200 | [diff] [blame] | 550 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 551 | pci_or_config8(HOST_BRIDGE, 0xf0, (1 << 2)); |
Arthur Heymans | bb5e77c | 2016-11-30 20:37:29 +0100 | [diff] [blame] | 552 | |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 553 | full_reset(); |
Arthur Heymans | bb5e77c | 2016-11-30 20:37:29 +0100 | [diff] [blame] | 554 | } |
| 555 | pmcon2 |= 0x80; |
| 556 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); |
| 557 | } |
| 558 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 559 | /** |
| 560 | * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 |
| 561 | */ |
| 562 | void sdram_initialize(int boot_path, const u8 *spd_map) |
| 563 | { |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 564 | struct sysinfo s, *ctrl_cached; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 565 | u8 reg8; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 566 | int fast_boot, cbmem_was_inited; |
| 567 | size_t mrc_size; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 568 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 569 | timestamp_add_now(TS_INITRAM_START); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 570 | printk(BIOS_DEBUG, "Setting up RAM controller.\n"); |
| 571 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 572 | pci_write_config8(HOST_BRIDGE, 0xdf, 0xff); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 573 | |
| 574 | memset(&s, 0, sizeof(struct sysinfo)); |
| 575 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 576 | ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 577 | MRC_CACHE_VERSION, |
| 578 | &mrc_size); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 579 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 580 | if (!ctrl_cached || mrc_size < sizeof(s)) { |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 581 | if (boot_path == BOOT_PATH_RESUME) { |
| 582 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | b559b3c | 2019-04-28 17:52:10 +0200 | [diff] [blame] | 583 | system_reset(); |
Arthur Heymans | df946b8 | 2018-06-14 10:53:51 +0200 | [diff] [blame] | 584 | } else if (boot_path == BOOT_PATH_WARM_RESET) { |
| 585 | /* On warm reset some of dram calibrations fail |
| 586 | and therefore requiring valid cached settings */ |
Elyes HAOUAS | b559b3c | 2019-04-28 17:52:10 +0200 | [diff] [blame] | 587 | full_reset(); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 588 | } |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 589 | } |
Arthur Heymans | bb5e77c | 2016-11-30 20:37:29 +0100 | [diff] [blame] | 590 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 591 | /* verify MRC cache for fast boot */ |
| 592 | if (boot_path != BOOT_PATH_RESUME && ctrl_cached) { |
Angel Pons | 9d20c84 | 2021-01-13 12:39:37 +0100 | [diff] [blame] | 593 | /* check SPD checksum to make sure the DIMMs haven't been replaced */ |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 594 | fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS; |
Arthur Heymans | b0c6cff | 2018-09-05 20:39:39 +0200 | [diff] [blame] | 595 | if (!fast_boot) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 596 | printk(BIOS_DEBUG, |
| 597 | "SPD checksums don't match, dimm's have been replaced\n"); |
Arthur Heymans | b0c6cff | 2018-09-05 20:39:39 +0200 | [diff] [blame] | 598 | } else { |
| 599 | find_fsb_speed(&s); |
| 600 | fast_boot = s.max_fsb == ctrl_cached->max_fsb; |
| 601 | if (!fast_boot) |
| 602 | printk(BIOS_DEBUG, |
| 603 | "CPU FSB does not match and has been replaced\n"); |
| 604 | } |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 605 | } else { |
| 606 | fast_boot = boot_path == BOOT_PATH_RESUME; |
| 607 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 608 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 609 | if (fast_boot) { |
| 610 | printk(BIOS_DEBUG, "Using cached raminit settings\n"); |
| 611 | memcpy(&s, ctrl_cached, sizeof(s)); |
| 612 | s.boot_path = boot_path; |
| 613 | mchinfo_ddr2(&s); |
| 614 | print_selected_timings(&s); |
| 615 | } else { |
| 616 | s.boot_path = boot_path; |
| 617 | s.spd_map[0] = spd_map[0]; |
| 618 | s.spd_map[1] = spd_map[1]; |
| 619 | s.spd_map[2] = spd_map[2]; |
| 620 | s.spd_map[3] = spd_map[3]; |
| 621 | checkreset_ddr2(s.boot_path); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 622 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 623 | /* Detect dimms per channel */ |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 624 | reg8 = pci_read_config8(HOST_BRIDGE, 0xe9); |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 625 | printk(BIOS_DEBUG, "Dimms per channel: %d\n", (reg8 & 0x10) ? 1 : 2); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 626 | |
| 627 | mchinfo_ddr2(&s); |
| 628 | |
| 629 | find_fsb_speed(&s); |
| 630 | decode_spd_select_timings(&s); |
| 631 | print_selected_timings(&s); |
| 632 | find_dimm_config(&s); |
| 633 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 634 | |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 635 | do_raminit(&s, fast_boot); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 636 | |
Angel Pons | 4a9569a | 2020-06-08 01:39:25 +0200 | [diff] [blame] | 637 | pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 638 | |
Angel Pons | d1c590a | 2020-08-03 16:01:39 +0200 | [diff] [blame] | 639 | pci_or_config8(HOST_BRIDGE, 0xf4, 1); |
Angel Pons | 4a9569a | 2020-06-08 01:39:25 +0200 | [diff] [blame] | 640 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 641 | timestamp_add_now(TS_INITRAM_END); |
Kyösti Mälkki | b33c6fb | 2021-02-17 20:43:04 +0200 | [diff] [blame] | 642 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 643 | printk(BIOS_DEBUG, "RAM initialization finished.\n"); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 644 | |
Kyösti Mälkki | 3051a9e | 2021-02-17 20:43:04 +0200 | [diff] [blame] | 645 | int s3resume = boot_path == BOOT_PATH_RESUME; |
| 646 | |
| 647 | cbmem_was_inited = !cbmem_recovery(s3resume); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 648 | if (!fast_boot) |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 649 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &s, sizeof(s)); |
Kyösti Mälkki | 3051a9e | 2021-02-17 20:43:04 +0200 | [diff] [blame] | 650 | |
| 651 | if (s3resume && !cbmem_was_inited) { |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 652 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | b559b3c | 2019-04-28 17:52:10 +0200 | [diff] [blame] | 653 | system_reset(); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 654 | } |
Elyes HAOUAS | f5a57a8 | 2019-01-08 22:15:53 +0100 | [diff] [blame] | 655 | |
Elyes HAOUAS | f5a57a8 | 2019-01-08 22:15:53 +0100 | [diff] [blame] | 656 | printk(BIOS_DEBUG, "Memory initialized\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 657 | } |