nb/intel/x4x: Use new fixed BAR accessors
Some cases break reproducibility if refactored, and are left as-is.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 5f937cf..460916b 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -412,7 +412,7 @@
static void find_fsb_speed(struct sysinfo *s)
{
- switch ((MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
+ switch ((mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
case 0x0:
s->max_fsb = FSB_CLOCK_1066MHz;
break;
@@ -532,7 +532,7 @@
u32 pmsts;
if (boot_path >= 1) {
- pmsts = MCHBAR32(PMSTS_MCHBAR);
+ pmsts = mchbar_read32(PMSTS_MCHBAR);
if (!(pmsts & 1))
printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n");
if (!(pmsts & 2))