Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <cbmem.h> |
| 19 | #include <console/console.h> |
| 20 | #include <cpu/x86/cache.h> |
| 21 | #include <cpu/x86/mtrr.h> |
| 22 | #include <delay.h> |
| 23 | #include <halt.h> |
| 24 | #include <lib.h> |
| 25 | #include <northbridge/intel/x4x/x4x.h> |
| 26 | #include <pc80/mc146818rtc.h> |
| 27 | #include <spd.h> |
| 28 | #include <string.h> |
| 29 | |
| 30 | static inline int spd_read_byte(unsigned int device, unsigned int address) |
| 31 | { |
| 32 | return smbus_read_byte(device, address); |
| 33 | } |
| 34 | |
| 35 | static void sdram_read_spds(struct sysinfo *s) |
| 36 | { |
| 37 | u8 i, j, chan; |
| 38 | int status = 0; |
| 39 | FOR_EACH_DIMM(i) { |
| 40 | if (s->spd_map[i] == 0) { |
| 41 | /* Non-existant SPD address */ |
| 42 | s->dimms[i].card_type = 0; |
| 43 | continue; |
| 44 | } |
| 45 | for (j = 0; j < 64; j++) { |
| 46 | status = spd_read_byte(s->spd_map[i], j); |
| 47 | if (status < 0) { |
| 48 | /* No SPD here */ |
| 49 | s->dimms[i].card_type = 0; |
| 50 | break; |
| 51 | } |
| 52 | s->dimms[i].spd_data[j] = (u8) status; |
| 53 | if (j == 62) |
| 54 | s->dimms[i].card_type = ((u8) status) & 0x1f; |
| 55 | } |
| 56 | if (status >= 0) { |
| 57 | hexdump(s->dimms[i].spd_data, 64); |
| 58 | } |
| 59 | } |
| 60 | |
| 61 | s->spd_type = 0; |
| 62 | int fail = 1; |
| 63 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 64 | switch ((enum ddrxspd) s->dimms[i].spd_data[2]) { |
| 65 | case DDR2SPD: |
| 66 | if (s->spd_type == 0) { |
| 67 | s->spd_type = DDR2; |
| 68 | } else if (s->spd_type == DDR3) { |
| 69 | die("DIMM type mismatch\n"); |
| 70 | } |
| 71 | break; |
| 72 | case DDR3SPD: |
| 73 | default: |
| 74 | if (s->spd_type == 0) { |
| 75 | s->spd_type = DDR3; |
| 76 | } else if (s->spd_type == DDR2) { |
| 77 | die("DIMM type mismatch\n"); |
| 78 | } |
| 79 | break; |
| 80 | } |
| 81 | } |
| 82 | if (s->spd_type == DDR3) { |
| 83 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 84 | s->dimms[i].sides = (s->dimms[i].spd_data[5] & 0x0f) + 1; |
| 85 | s->dimms[i].ranks = ((s->dimms[i].spd_data[7] >> 3) & 0x7) + 1; |
| 86 | s->dimms[i].chip_capacity = (s->dimms[i].spd_data[4] & 0xf); |
| 87 | s->dimms[i].banks = 8; |
| 88 | s->dimms[i].rows = ((s->dimms[i].spd_data[5] >> 3) & 0x7) + 12; |
| 89 | s->dimms[i].cols = (s->dimms[i].spd_data[5] & 0x7) + 9; |
| 90 | s->dimms[i].cas_latencies = 0xfe; |
| 91 | s->dimms[i].cas_latencies &= (s->dimms[i].spd_data[14] << 1); |
| 92 | if (s->dimms[i].cas_latencies == 0) |
| 93 | s->dimms[i].cas_latencies = 0x40; |
| 94 | s->dimms[i].tAAmin = s->dimms[i].spd_data[16]; |
| 95 | s->dimms[i].tCKmin = s->dimms[i].spd_data[12]; |
| 96 | s->dimms[i].width = s->dimms[i].spd_data[7] & 0x7; |
| 97 | s->dimms[i].page_size = s->dimms[i].width * (1 << s->dimms[i].cols); // Bytes |
| 98 | s->dimms[i].tRAS = ((s->dimms[i].spd_data[21] & 0xf) << 8) | |
| 99 | s->dimms[i].spd_data[22]; |
| 100 | s->dimms[i].tRP = s->dimms[i].spd_data[20]; |
| 101 | s->dimms[i].tRCD = s->dimms[i].spd_data[18]; |
| 102 | s->dimms[i].tWR = s->dimms[i].spd_data[17]; |
| 103 | fail = 0; |
| 104 | } |
| 105 | } else if (s->spd_type == DDR2) { |
| 106 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 107 | s->dimms[i].sides = (s->dimms[i].spd_data[5] & 0x7) + 1; |
| 108 | s->dimms[i].banks = (s->dimms[i].spd_data[17] >> 2) - 1; |
| 109 | s->dimms[i].chip_capacity = s->dimms[i].banks; |
| 110 | s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12; |
| 111 | s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9; |
| 112 | s->dimms[i].cas_latencies = 0x78; |
| 113 | s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18]; |
| 114 | if (s->dimms[i].cas_latencies == 0) |
| 115 | s->dimms[i].cas_latencies = 7; |
| 116 | s->dimms[i].tAAmin = s->dimms[i].spd_data[26]; |
| 117 | s->dimms[i].tCKmin = s->dimms[i].spd_data[25]; |
| 118 | s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1; |
| 119 | s->dimms[i].page_size = (s->dimms[i].width+1) * (1 << s->dimms[i].cols); // Bytes |
| 120 | s->dimms[i].tRAS = s->dimms[i].spd_data[30]; |
| 121 | s->dimms[i].tRP = s->dimms[i].spd_data[27]; |
| 122 | s->dimms[i].tRCD = s->dimms[i].spd_data[29]; |
| 123 | s->dimms[i].tWR = s->dimms[i].spd_data[36]; |
| 124 | s->dimms[i].ranks = s->dimms[i].sides; // XXX |
| 125 | |
| 126 | printk(BIOS_DEBUG, "DIMM %d\n", i); |
| 127 | printk(BIOS_DEBUG, " Sides : %d\n", s->dimms[i].sides); |
| 128 | printk(BIOS_DEBUG, " Banks : %d\n", s->dimms[i].banks); |
| 129 | printk(BIOS_DEBUG, " Ranks : %d\n", s->dimms[i].ranks); |
| 130 | printk(BIOS_DEBUG, " Rows : %d\n", s->dimms[i].rows); |
| 131 | printk(BIOS_DEBUG, " Cols : %d\n", s->dimms[i].cols); |
| 132 | printk(BIOS_DEBUG, " Page size : %d\n", s->dimms[i].page_size); |
| 133 | printk(BIOS_DEBUG, " Width : %d\n", (s->dimms[i].width+1)*8); |
| 134 | fail = 0; |
| 135 | } |
| 136 | } |
| 137 | if (fail) { |
| 138 | die("No memory dimms, halt\n"); |
| 139 | } |
| 140 | |
| 141 | FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) { |
| 142 | if (s->dimms[chan>>1].sides == 0) { |
| 143 | // NC |
| 144 | if (s->dimms[(chan>>1) + 1].sides == 0) { |
| 145 | // NC/NC |
| 146 | s->dimm_config[chan] = 0; |
| 147 | } else if (s->dimms[(chan>>1) + 1].sides == 1) { |
| 148 | // NC/SS |
| 149 | if (s->dimms[(chan>>1) + 1].width == 0) { |
| 150 | // NC/8SS |
| 151 | s->dimm_config[chan] = 4; |
| 152 | } else { |
| 153 | // NC/16SS |
| 154 | s->dimm_config[chan] = 12; |
| 155 | } |
| 156 | } else { |
| 157 | // NC/DS |
| 158 | if (s->dimms[(chan>>1) + 1].width == 0) { |
| 159 | // NC/8DS |
| 160 | s->dimm_config[chan] = 8; |
| 161 | } else { |
| 162 | // NOT SUPPORTED |
| 163 | die("16DS Not supported\n"); |
| 164 | } |
| 165 | } |
| 166 | } else if (s->dimms[chan>>1].sides == 1) { |
| 167 | // SS |
| 168 | if (s->dimms[(chan>>1) + 1].sides == 0) { |
| 169 | // SS/NC |
| 170 | if (s->dimms[chan>>1].width == 0) { |
| 171 | // 8SS/NC |
| 172 | s->dimm_config[chan] = 1; |
| 173 | } else { |
| 174 | // 16SS/NC |
| 175 | s->dimm_config[chan] = 3; |
| 176 | } |
| 177 | } else if (s->dimms[(chan>>1) + 1].sides == 1) { |
| 178 | // SS/SS |
| 179 | if (s->dimms[chan>>1].width == 0) { |
| 180 | if (s->dimms[(chan>>1) + 1].width == 0) { |
| 181 | // 8SS/8SS |
| 182 | s->dimm_config[chan] = 5; |
| 183 | } else { |
| 184 | // 8SS/16SS |
| 185 | s->dimm_config[chan] = 13; |
| 186 | } |
| 187 | } else { |
| 188 | if (s->dimms[(chan>>1) + 1].width == 0) { |
| 189 | // 16SS/8SS |
| 190 | s->dimm_config[chan] = 7; |
| 191 | } else { |
| 192 | // 16SS/16SS |
| 193 | s->dimm_config[chan] = 15; |
| 194 | } |
| 195 | } |
| 196 | } else { |
| 197 | // SS/DS |
| 198 | if (s->dimms[chan>>1].width == 0) { |
| 199 | if (s->dimms[(chan>>1) + 1].width == 0) { |
| 200 | // 8SS/8DS |
| 201 | s->dimm_config[chan] = 9; |
| 202 | } else { |
| 203 | die("16DS not supported\n"); |
| 204 | } |
| 205 | } else { |
| 206 | if (s->dimms[(chan>>1) + 1].width == 0) { |
| 207 | // 16SS/8DS |
| 208 | s->dimm_config[chan] = 11; |
| 209 | } else { |
| 210 | die("16DS not supported\n"); |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | } else { |
| 215 | // DS |
| 216 | if (s->dimms[(chan>>1) + 1].sides == 0) { |
| 217 | // DS/NC |
| 218 | if (s->dimms[chan>>1].width == 0) { |
| 219 | // 8DS/NC |
| 220 | s->dimm_config[chan] = 2; |
| 221 | } else { |
| 222 | die("16DS not supported\n"); |
| 223 | } |
| 224 | } else if (s->dimms[(chan>>1) + 1].sides == 1) { |
| 225 | // DS/SS |
| 226 | if (s->dimms[chan>>1].width == 0) { |
| 227 | if (s->dimms[(chan>>1) + 1].width == 0) { |
| 228 | // 8DS/8SS |
| 229 | s->dimm_config[chan] = 6; |
| 230 | } else { |
| 231 | // 8DS/16SS |
| 232 | s->dimm_config[chan] = 14; |
| 233 | } |
| 234 | } else { |
| 235 | die("16DS not supported\n"); |
| 236 | } |
| 237 | } else { |
| 238 | // DS/DS |
| 239 | if (s->dimms[chan>>1].width == 0 && s->dimms[(chan>>1)+1].width == 0) { |
| 240 | // 8DS/8DS |
| 241 | s->dimm_config[chan] = 10; |
| 242 | } |
| 243 | } |
| 244 | } |
| 245 | printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | static u8 lsbpos(u8 val) //Forward |
| 250 | { |
| 251 | u8 i; |
| 252 | for (i = 0; (i < 8) && ((val & (1 << i)) == 0); i++); |
| 253 | return i; |
| 254 | } |
| 255 | |
| 256 | static u8 msbpos(u8 val) //Reverse |
| 257 | { |
| 258 | u8 i; |
| 259 | for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); |
| 260 | return i; |
| 261 | } |
| 262 | |
| 263 | static void mchinfo_ddr2(struct sysinfo *s) |
| 264 | { |
| 265 | const u32 eax = cpuid_ext(0x04, 0).eax; |
| 266 | s->cores = ((eax >> 26) & 0x3f) + 1; |
| 267 | printk(BIOS_WARNING, "%d CPU cores\n", s->cores); |
| 268 | |
| 269 | u32 capid = pci_read_config16(PCI_DEV(0,0,0), 0xe8); |
| 270 | if (!(capid & (1<<(79-64)))) { |
| 271 | printk(BIOS_WARNING, "iTPM enabled\n"); |
| 272 | } |
| 273 | |
| 274 | capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); |
| 275 | if (!(capid & (1<<(57-32)))) { |
| 276 | printk(BIOS_WARNING, "ME enabled\n"); |
| 277 | } |
| 278 | |
| 279 | if (!(capid & (1<<(56-32)))) { |
| 280 | printk(BIOS_WARNING, "AMT enabled\n"); |
| 281 | } |
| 282 | |
| 283 | s->max_ddr2_mhz = (capid & (1<<(53-32)))?667:800; |
| 284 | printk(BIOS_WARNING, "Capable of DDR2 of %d MHz or lower\n", s->max_ddr2_mhz); |
| 285 | |
| 286 | if (!(capid & (1<<(48-32)))) { |
| 287 | printk(BIOS_WARNING, "VT-d enabled\n"); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | static void sdram_detect_ram_speed(struct sysinfo *s) |
| 292 | { |
| 293 | u8 i; |
| 294 | u8 commoncas = 0; |
| 295 | u8 cas; |
| 296 | u8 lowcas; |
| 297 | u8 highcas; |
| 298 | u8 maxfreq; |
| 299 | u8 freq = 0; |
| 300 | |
| 301 | // Find max FSB speed |
| 302 | switch (MCHBAR32(0xc00) & 0x7) { |
| 303 | case 0x0: |
| 304 | s->max_fsb = FSB_CLOCK_1066MHz; |
| 305 | break; |
| 306 | case 0x2: |
| 307 | s->max_fsb = FSB_CLOCK_800MHz; |
| 308 | break; |
| 309 | case 0x4: |
| 310 | s->max_fsb = FSB_CLOCK_1333MHz; |
| 311 | break; |
| 312 | default: |
| 313 | s->max_fsb = FSB_CLOCK_800MHz; |
| 314 | printk(BIOS_WARNING, "Can't detect FSB, setting 800MHz\n"); |
| 315 | break; |
| 316 | } |
| 317 | |
| 318 | // Find RAM speed |
| 319 | maxfreq = (u8) ((pci_read_config16(PCI_DEV(0,0,0), 0xea) >> 4) & 0x3f); |
| 320 | if (s->spd_type == DDR2) { |
| 321 | |
| 322 | // Limit frequency for MCH |
| 323 | maxfreq &= 0x7; |
| 324 | freq = MEM_CLOCK_800MHz; |
| 325 | if (maxfreq) { |
| 326 | freq = maxfreq; |
| 327 | } |
| 328 | if (freq > MEM_CLOCK_800MHz) { |
| 329 | freq = MEM_CLOCK_800MHz; |
| 330 | } |
| 331 | |
| 332 | // Detect a common CAS latency |
| 333 | commoncas = 0xff; |
| 334 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 335 | commoncas &= s->dimms[i].spd_data[18]; |
| 336 | } |
| 337 | if (commoncas == 0) { |
| 338 | die("No common CAS among dimms\n"); |
| 339 | } |
| 340 | |
| 341 | // Start with fastest common CAS |
| 342 | cas = 0; |
| 343 | highcas = msbpos(commoncas); |
| 344 | lowcas = lsbpos(commoncas); |
| 345 | |
| 346 | while (cas == 0 && highcas >= lowcas) { |
| 347 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 348 | switch (freq) { |
| 349 | case MEM_CLOCK_800MHz: |
| 350 | if ((s->dimms[i].spd_data[9] > 0x25) || |
| 351 | (s->dimms[i].spd_data[10] > 0x40)) { |
| 352 | // CAS too fast, lower it |
| 353 | highcas--; |
| 354 | break; |
| 355 | } else { |
| 356 | cas = highcas; |
| 357 | } |
| 358 | break; |
| 359 | case MEM_CLOCK_667MHz: |
| 360 | default: |
| 361 | if ((s->dimms[i].spd_data[9] > 0x30) || |
| 362 | (s->dimms[i].spd_data[10] > 0x45)) { |
| 363 | // CAS too fast, lower it |
| 364 | highcas--; |
| 365 | break; |
| 366 | } else { |
| 367 | cas = highcas; |
| 368 | } |
| 369 | break; |
| 370 | } |
| 371 | } |
| 372 | } |
| 373 | if (highcas < lowcas) { |
| 374 | // Timings not supported by MCH, lower the frequency |
| 375 | freq--; |
| 376 | cas = 0; |
| 377 | highcas = msbpos(commoncas); |
| 378 | lowcas = lsbpos(commoncas); |
| 379 | while (cas == 0 && highcas >= lowcas) { |
| 380 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 381 | switch (freq) { |
| 382 | case MEM_CLOCK_800MHz: |
| 383 | if ((s->dimms[i].spd_data[23] > 0x25) || |
| 384 | (s->dimms[i].spd_data[24] > 0x40)) { |
| 385 | // CAS too fast, lower it |
| 386 | highcas--; |
| 387 | break; |
| 388 | } else { |
| 389 | cas = highcas; |
| 390 | } |
| 391 | break; |
| 392 | case MEM_CLOCK_667MHz: |
| 393 | default: |
| 394 | if ((s->dimms[i].spd_data[23] > 0x30) || |
| 395 | (s->dimms[i].spd_data[24] > 0x45)) { |
| 396 | // CAS too fast, lower it |
| 397 | highcas--; |
| 398 | break; |
| 399 | } else { |
| 400 | cas = highcas; |
| 401 | } |
| 402 | break; |
| 403 | } |
| 404 | } |
| 405 | } |
| 406 | } |
| 407 | s->selected_timings.mem_clk = freq; |
| 408 | s->selected_timings.CAS = cas; |
| 409 | |
| 410 | } else { // DDR3 |
| 411 | // Limit frequency for MCH |
| 412 | maxfreq >>= 3; |
| 413 | freq = MEM_CLOCK_1333MHz; |
| 414 | if (maxfreq) { |
| 415 | freq = maxfreq + 2; |
| 416 | } |
| 417 | if (freq > MEM_CLOCK_1333MHz) { |
| 418 | freq = MEM_CLOCK_1333MHz; |
| 419 | } |
| 420 | |
| 421 | // Limit DDR speed to FSB speed |
| 422 | switch (s->max_fsb) { |
| 423 | case FSB_CLOCK_800MHz: |
| 424 | if (freq > MEM_CLOCK_800MHz) { |
| 425 | freq = MEM_CLOCK_800MHz; |
| 426 | } |
| 427 | break; |
| 428 | case FSB_CLOCK_1066MHz: |
| 429 | if (freq > MEM_CLOCK_1066MHz) { |
| 430 | freq = MEM_CLOCK_1066MHz; |
| 431 | } |
| 432 | break; |
| 433 | case FSB_CLOCK_1333MHz: |
| 434 | if (freq > MEM_CLOCK_1333MHz) { |
| 435 | freq = MEM_CLOCK_1333MHz; |
| 436 | } |
| 437 | break; |
| 438 | default: |
| 439 | die("Invalid FSB\n"); |
| 440 | break; |
| 441 | } |
| 442 | |
| 443 | // TODO: CAS detection for DDR3 |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | /** |
| 448 | * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 |
| 449 | */ |
| 450 | void sdram_initialize(int boot_path, const u8 *spd_map) |
| 451 | { |
| 452 | struct sysinfo s; |
| 453 | u8 reg8; |
| 454 | |
| 455 | printk(BIOS_DEBUG, "Setting up RAM controller.\n"); |
| 456 | |
| 457 | pci_write_config8(PCI_DEV(0,0,0), 0xdf, 0xff); |
| 458 | |
| 459 | memset(&s, 0, sizeof(struct sysinfo)); |
| 460 | |
| 461 | s.boot_path = boot_path; |
| 462 | s.spd_map[0] = spd_map[0]; |
| 463 | s.spd_map[1] = spd_map[1]; |
| 464 | s.spd_map[2] = spd_map[2]; |
| 465 | s.spd_map[3] = spd_map[3]; |
| 466 | |
| 467 | /* Detect dimms per channel */ |
| 468 | s.dimms_per_ch = 2; |
| 469 | reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xe9); |
| 470 | if (reg8 & 0x10) |
| 471 | s.dimms_per_ch = 1; |
| 472 | |
| 473 | printk(BIOS_DEBUG, "Dimms per channel: %d\n", s.dimms_per_ch); |
| 474 | |
| 475 | mchinfo_ddr2(&s); |
| 476 | |
| 477 | sdram_read_spds(&s); |
| 478 | |
| 479 | /* Choose Common Frequency */ |
| 480 | sdram_detect_ram_speed(&s); |
| 481 | |
| 482 | switch (s.spd_type) { |
| 483 | case DDR2: |
| 484 | raminit_ddr2(&s); |
| 485 | break; |
| 486 | case DDR3: |
| 487 | // FIXME Add: raminit_ddr3(&s); |
| 488 | break; |
| 489 | default: |
| 490 | die("Unknown DDR type\n"); |
| 491 | break; |
| 492 | } |
| 493 | |
| 494 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
| 495 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80); |
| 496 | |
| 497 | reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf4); |
| 498 | pci_write_config8(PCI_DEV(0,0,0), 0xf4, reg8 | 1); |
| 499 | printk(BIOS_DEBUG, "RAM initialization finished.\n"); |
| 500 | } |