Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BRASWELL |
| 2 | bool |
| 3 | help |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 4 | Braswell M/D part support. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 5 | |
| 6 | if SOC_INTEL_BRASWELL |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 11 | select ARCH_ALL_STAGES_X86_32 |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 14 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 16 | select HAVE_SMI_HANDLER |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | select PARALLEL_MP |
| 18 | select PCIEXP_ASPM |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 19 | select PCIEXP_CLK_PM |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | select PCIEXP_COMMON_CLOCK |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 21 | select PLATFORM_USES_FSP1_1 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | select REG_SCRIPT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 23 | select RTC |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 24 | select SOC_INTEL_COMMON |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 25 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Frans Hendriks | 59ae2ef | 2019-02-28 15:16:00 +0100 | [diff] [blame] | 26 | select SOC_INTEL_COMMON_BLOCK |
| 27 | select SOC_INTEL_COMMON_BLOCK_HDA |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 28 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 29 | select SPI_FLASH |
| 30 | select SSE2 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 31 | select TSC_MONOTONIC_TIMER |
| 32 | select TSC_SYNC_MFENCE |
| 33 | select UDELAY_TSC |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 34 | select USE_GENERIC_FSP_CAR_INC |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 35 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Martin Roth | 3a54318 | 2015-09-28 15:27:24 -0600 | [diff] [blame] | 36 | select HAVE_SPI_CONSOLE_SUPPORT |
Nico Huber | 2e7f6cc | 2017-05-22 15:58:03 +0200 | [diff] [blame] | 37 | select HAVE_FSP_GOP |
Matt DeVillier | 51ee7ce | 2017-08-20 18:21:10 -0500 | [diff] [blame] | 38 | select GENERIC_GPIO_LIB |
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 39 | select INTEL_GMA_ACPI |
| 40 | select INTEL_GMA_SWSMISCI |
Matt DeVillier | d3d0f07 | 2018-11-10 17:44:36 -0600 | [diff] [blame] | 41 | select CPU_INTEL_COMMON |
Frans Hendriks | b27fb33 | 2019-03-04 08:02:43 +0100 | [diff] [blame] | 42 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Arthur Heymans | 56d913e | 2019-06-04 14:45:13 +0200 | [diff] [blame] | 43 | select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 44 | |
| 45 | config DCACHE_BSP_STACK_SIZE |
| 46 | hex |
| 47 | default 0x2000 |
| 48 | help |
| 49 | The amount of anticipated stack usage in CAR by bootblock and |
| 50 | other stages. |
| 51 | |
| 52 | config C_ENV_BOOTBLOCK_SIZE |
| 53 | hex |
| 54 | default 0x8000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 55 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 56 | config VBOOT |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 57 | select VBOOT_MUST_REQUEST_DISPLAY |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 58 | select VBOOT_STARTS_IN_ROMSTAGE |
| 59 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 60 | config MMCONF_BASE_ADDRESS |
Arthur Heymans | 9c27eda | 2017-06-13 14:47:28 +0200 | [diff] [blame] | 61 | hex |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 62 | default 0xe0000000 |
| 63 | |
| 64 | config MAX_CPUS |
| 65 | int |
| 66 | default 4 |
| 67 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 68 | config SMM_TSEG_SIZE |
| 69 | hex |
| 70 | default 0x800000 |
| 71 | |
| 72 | config SMM_RESERVED_SIZE |
| 73 | hex |
| 74 | default 0x100000 |
| 75 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 76 | # Cache As RAM region layout: |
| 77 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 78 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
Kyösti Mälkki | 2bad1e7 | 2016-07-26 14:03:31 +0300 | [diff] [blame] | 79 | # | Stack | |
| 80 | # | | | |
| 81 | # | v | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 82 | # +-------------+ |
| 83 | # | ^ | |
| 84 | # | | | |
| 85 | # | CAR Globals | |
| 86 | # +-------------+ DCACHE_RAM_BASE |
| 87 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 88 | |
| 89 | config DCACHE_RAM_BASE |
Arthur Heymans | 9c27eda | 2017-06-13 14:47:28 +0200 | [diff] [blame] | 90 | hex |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 91 | default 0xfef00000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 92 | |
| 93 | config DCACHE_RAM_SIZE |
Arthur Heymans | 9c27eda | 2017-06-13 14:47:28 +0200 | [diff] [blame] | 94 | hex |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 95 | default 0x4000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 96 | help |
| 97 | The size of the cache-as-ram region required during bootblock |
| 98 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 99 | must add up to a power of 2. |
| 100 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 101 | config ENABLE_BUILTIN_COM1 |
| 102 | bool "Enable builtin COM1 Serial Port" |
| 103 | default n |
| 104 | help |
| 105 | The PMC has a legacy COM1 serial port. Choose this option to |
| 106 | configure the pads and enable it. This serial port can be used for |
| 107 | the debug console. |
| 108 | |
Frans Hendriks | f2af702 | 2018-11-16 12:08:41 +0100 | [diff] [blame] | 109 | config DISABLE_HPET |
| 110 | bool "Disable the HPET device" |
| 111 | default n |
| 112 | help |
| 113 | Enable this to disable the HPET support |
| 114 | Solves the Linux MP-BIOS bug timer not connected. |
| 115 | |
Matt DeVillier | fd7440d | 2019-04-23 12:21:17 -0500 | [diff] [blame] | 116 | config USE_GOOGLE_FSP |
| 117 | bool |
| 118 | help |
| 119 | Select this to use Google's custom Braswell FSP header/binary |
| 120 | instead of the public release on Github. Only google/cyan |
| 121 | variants require this; all other boards should use the public release. |
| 122 | |
| 123 | config FSP_HEADER_PATH |
| 124 | string |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 125 | default "\$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP |
Matt DeVillier | fd7440d | 2019-04-23 12:21:17 -0500 | [diff] [blame] | 126 | default "3rdparty/fsp/BraswellFspBinPkg/Include/" |
| 127 | help |
| 128 | Location of FSP header file FspUpdVpd.h |
| 129 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 130 | endif |