Blame - src/southbridge/amd/pi/hudson/pci_devs.h - coreboot

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Angel Pons	182dbde	2020-04-02 23:49:05 +0200	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
				3	#ifndef _PI_HUDSON_PCI_DEVS_H_
				4	#define _PI_HUDSON_PCI_DEVS_H_
				5
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	6	#include <device/pci_def.h>
				7
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	8	/* XHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	9	#define XHCI_DEV 0x10
				10	#define XHCI_FUNC 0
				11	#define XHCI_DEVID 0x7814
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	12	#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	13
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	14	#define XHCI2_DEV 0x10
				15	#define XHCI2_FUNC 1
				16	#define XHCI2_DEVID 0x7814
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	17	#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
Dave Frodin	9cfa742	2015-01-27 07:19:48 -0700	[diff] [blame]	18
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	19	/* SATA */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	20	#define SATA_DEV 0x11
				21	#define SATA_FUNC 0
				22	#define SATA_IDE_DEVID 0x7800
				23	#define AHCI_DEVID_MS 0x7801
				24	#define AHCI_DEVID_AMD 0x7804
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	25	#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	26
				27	/* OHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	28	#define OHCI1_DEV 0x12
				29	#define OHCI1_FUNC 0
				30	#define OHCI2_DEV 0x13
				31	#define OHCI2_FUNC 0
				32	#define OHCI3_DEV 0x16
				33	#define OHCI3_FUNC 0
				34	#define OHCI4_DEV 0x14
				35	#define OHCI4_FUNC 5
				36	#define OHCI_DEVID 0x7807
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	37	#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
				38	#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
				39	#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
				40	#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	41
				42	/* EHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	43	#define EHCI1_DEV 0x12
				44	#define EHCI1_FUNC 2
				45	#define EHCI2_DEV 0x13
				46	#define EHCI2_FUNC 2
				47	#define EHCI3_DEV 0x16
				48	#define EHCI3_FUNC 2
				49	#define EHCI_DEVID 0x7808
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	50	#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
				51	#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
				52	#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	53
				54	/* SMBUS */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	55	#define SMBUS_DEV 0x14
				56	#define SMBUS_FUNC 0
				57	#define SMBUS_DEVID 0x780B
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	58	#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	59
				60	/* HD Audio */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	61	#define HDA_DEV 0x14
				62	#define HDA_FUNC 2
				63	#define HDA_DEVID 0x780D
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	64	#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	65
				66	/* LPC BUS */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	67	#define PCU_DEV 0x14
Philipp Deppenwiese	3067012	2017-03-01 02:24:33 +0100	[diff] [blame]	68	#define LPC_DEV PCU_DEV
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	69	#define LPC_FUNC 3
				70	#define LPC_DEVID 0x780E
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	71	#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	72
				73	/* PCI Ports */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	74	#define SB_PCI_PORT_DEV 0x14
				75	#define SB_PCI_PORT_FUNC 4
				76	#define SB_PCI_PORT_DEVID 0x780F
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	77	#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	78
				79	/* SD Controller */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	80	#define SD_DEV 0x14
				81	#define SD_FUNC 7
				82	#define SD_DEVID 0x7806
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	83	#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	84
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	85	#endif /* _PI_HUDSON_PCI_DEVS_H_ */