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review.coreboot.org / coreboot / 182dbdeac4b2489f8d03a47a79ab28ad556d9d21 / . / src / southbridge / amd / pi / hudson / pci_devs.h
blob: 0a51a4f253789ab6035a4410a274de569e45a3ba [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]3
4#ifndef _PI_HUDSON_PCI_DEVS_H_
5#define _PI_HUDSON_PCI_DEVS_H_
6
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]7#define BUS0 0
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]8
9/* XHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]10#define XHCI_DEV 0x10
11#define XHCI_FUNC 0
12#define XHCI_DEVID 0x7814
13#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]14
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]15#define XHCI2_DEV 0x10
16#define XHCI2_FUNC 1
17#define XHCI2_DEVID 0x7814
18#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]19
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]20/* SATA */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]21#define SATA_DEV 0x11
22#define SATA_FUNC 0
23#define SATA_IDE_DEVID 0x7800
24#define AHCI_DEVID_MS 0x7801
25#define AHCI_DEVID_AMD 0x7804
26#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]27
28/* OHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]29#define OHCI1_DEV 0x12
30#define OHCI1_FUNC 0
31#define OHCI2_DEV 0x13
32#define OHCI2_FUNC 0
33#define OHCI3_DEV 0x16
34#define OHCI3_FUNC 0
35#define OHCI4_DEV 0x14
36#define OHCI4_FUNC 5
37#define OHCI_DEVID 0x7807
38#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
39#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
40#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
41#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]42
43/* EHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]44#define EHCI1_DEV 0x12
45#define EHCI1_FUNC 2
46#define EHCI2_DEV 0x13
47#define EHCI2_FUNC 2
48#define EHCI3_DEV 0x16
49#define EHCI3_FUNC 2
50#define EHCI_DEVID 0x7808
51#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
52#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
53#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]54
55/* SMBUS */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]56#define SMBUS_DEV 0x14
57#define SMBUS_FUNC 0
58#define SMBUS_DEVID 0x780B
59#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]60
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]61/* IDE */
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]62#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]63#define IDE_DEV 0x14
64#define IDE_FUNC 1
65#define IDE_DEVID 0x780C
66#define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]67#endif
68
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]69/* HD Audio */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]70#define HDA_DEV 0x14
71#define HDA_FUNC 2
72#define HDA_DEVID 0x780D
73#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]74
75/* LPC BUS */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]76#define PCU_DEV 0x14
Philipp Deppenwiese30670122017-03-01 02:24:33 +0100[diff] [blame]77#define LPC_DEV PCU_DEV
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]78#define LPC_FUNC 3
79#define LPC_DEVID 0x780E
80#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]81
82/* PCI Ports */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]83#define SB_PCI_PORT_DEV 0x14
84#define SB_PCI_PORT_FUNC 4
85#define SB_PCI_PORT_DEVID 0x780F
86#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]87
88/* SD Controller */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]89#define SD_DEV 0x14
90#define SD_FUNC 7
91#define SD_DEVID 0x7806
92#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]93
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]94/* PCIe Ports */
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]95#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]96#define SB_PCIE_DEV 0x15
97#define SB_PCIE_PORT1_FUNC 0
98#define SB_PCIE_PORT2_FUNC 1
99#define SB_PCIE_PORT3_FUNC 2
100#define SB_PCIE_PORT4_FUNC 3
101#define SB_PCIE_PORT1_DEVID 0x7820
102#define SB_PCIE_PORT2_DEVID 0x7821
103#define SB_PCIE_PORT3_DEVID 0x7822
104#define SB_PCIE_PORT4_DEVID 0x7823
105#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
106#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
107#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
108#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]109#endif
110
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]111#endif /* _PI_HUDSON_PCI_DEVS_H_ */