Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* coreboot UEFI PEI wrapper */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 3 | |
| 4 | #ifndef PEI_DATA_H |
| 5 | #define PEI_DATA_H |
| 6 | |
Elyes HAOUAS | c4e4193 | 2018-11-01 11:29:50 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 9 | typedef struct { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 10 | uint16_t mode; /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ |
| 11 | uint16_t hs_port_switch_mask; /* 4 bit mask, 1: switchable, 0: not switchable */ |
| 12 | uint16_t preboot_support; /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ |
| 13 | uint16_t xhci_streams; /* 0: Disable, 1: Enable */ |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 14 | } pch_usb3_controller_settings; |
| 15 | |
Vadim Bendebury | 48a4a7f | 2012-06-07 18:47:13 -0700 | [diff] [blame] | 16 | typedef void (*tx_byte_func)(unsigned char byte); |
Stefan Reinauer | 1cc3416 | 2013-06-27 15:59:18 -0700 | [diff] [blame] | 17 | #define PEI_VERSION 6 |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 18 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 19 | struct pei_data |
| 20 | { |
| 21 | uint32_t pei_version; |
| 22 | uint32_t mchbar; |
| 23 | uint32_t dmibar; |
| 24 | uint32_t epbar; |
| 25 | uint32_t pciexbar; |
| 26 | uint16_t smbusbar; |
| 27 | uint32_t wdbbar; |
| 28 | uint32_t wdbsize; |
| 29 | uint32_t hpet_address; |
| 30 | uint32_t rcba; |
| 31 | uint32_t pmbase; |
| 32 | uint32_t gpiobase; |
| 33 | uint32_t thermalbase; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 34 | uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 35 | uint32_t tseg_size; |
| 36 | uint8_t spd_addresses[4]; |
| 37 | uint8_t ts_addresses[4]; |
| 38 | int boot_mode; |
| 39 | int ec_present; |
Stefan Reinauer | 1cc3416 | 2013-06-27 15:59:18 -0700 | [diff] [blame] | 40 | int gbe_enable; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 41 | /* |
| 42 | * 0 = leave channel enabled |
| 43 | * 1 = disable dimm 0 on channel |
| 44 | * 2 = disable dimm 1 on channel |
| 45 | * 3 = disable dimm 0+1 on channel |
| 46 | */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 47 | int dimm_channel0_disabled; |
| 48 | int dimm_channel1_disabled; |
| 49 | /* Seed values saved in CMOS */ |
| 50 | uint32_t scrambler_seed; |
| 51 | uint32_t scrambler_seed_s3; |
| 52 | /* Data read from flash and passed into MRC */ |
| 53 | unsigned char *mrc_input; |
| 54 | unsigned int mrc_input_len; |
| 55 | /* Data from MRC that should be saved to flash */ |
| 56 | unsigned char *mrc_output; |
| 57 | unsigned int mrc_output_len; |
| 58 | /* |
| 59 | * Max frequency DDR3 could be ran at. Could be one of four values: |
| 60 | * 800, 1067, 1333, 1600 |
| 61 | */ |
| 62 | uint32_t max_ddr3_freq; |
| 63 | /* |
| 64 | * USB Port Configuration: |
| 65 | * [0] = enable |
| 66 | * [1] = overcurrent pin |
| 67 | * [2] = length |
| 68 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 69 | * Ports 0-7 can be mapped to OC0-OC3 |
Marc Jones | 53508fe | 2012-07-11 16:30:28 -0600 | [diff] [blame] | 70 | * Ports 8-13 can be mapped to OC4-OC7 |
| 71 | * |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 72 | * Port Length |
| 73 | * MOBILE: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 74 | * < 0x050 = Setting 1 (back panel, 1 to 5 in, lowest tx amplitude) |
| 75 | * < 0x140 = Setting 2 (back panel, 5 to 14 in, highest tx amplitude) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 76 | * DESKTOP: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 77 | * < 0x080 = Setting 1 (front/back panel, less than 8 in, lowest tx amplitude) |
| 78 | * < 0x130 = Setting 2 (back panel, 8 to 13 in, higher tx amplitude) |
| 79 | * < 0x150 = Setting 3 (back panel, 13 to 15 in, highest tx amplitude) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 80 | */ |
| 81 | uint16_t usb_port_config[16][3]; |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 82 | /* See the usb3 struct above for details */ |
| 83 | pch_usb3_controller_settings usb3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 84 | /* |
| 85 | * SPD data array for onboard RAM. Note that spd_data [1..3] are ignored: instead, |
| 86 | * the "dimm_channel{0,1}_disabled" flag and the spd_addresses are used to determine |
| 87 | * which DIMMs should use the SPD from spd_data[0]. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 88 | */ |
| 89 | uint8_t spd_data[4][256]; |
Vadim Bendebury | 48a4a7f | 2012-06-07 18:47:13 -0700 | [diff] [blame] | 90 | tx_byte_func tx_byte; |
Duncan Laurie | e8179b5 | 2012-07-11 10:40:45 -0700 | [diff] [blame] | 91 | int ddr3lv_support; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 92 | /* |
| 93 | * pcie_init needs to be set to 1 to have the system agent initialize PCIe. |
| 94 | * Note: This should only be required if your system has Gen3 devices and |
| 95 | * it will increase your boot time by at least 100ms. |
Stefan Reinauer | 7e8c8e9 | 2012-09-04 10:59:29 -0700 | [diff] [blame] | 96 | */ |
| 97 | int pcie_init; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 98 | /* |
| 99 | * N mode functionality. Leave this setting at 0. |
| 100 | * |
| 101 | * 0: Auto |
| 102 | * 1: 1N |
| 103 | * 2: 2N |
Stefan Reinauer | 7e8c8e9 | 2012-09-04 10:59:29 -0700 | [diff] [blame] | 104 | */ |
| 105 | int nmode; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 106 | /* |
| 107 | * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to |
| 108 | * specify whether double-rate is required for extended operating temperature range. |
| 109 | * |
| 110 | * 0: Enable double rate based upon temperature thresholds |
| 111 | * 1: Normal rate |
| 112 | * 2: Always enable double rate |
Shawn Nematbakhsh | 932fbd6 | 2013-05-08 11:41:04 -0700 | [diff] [blame] | 113 | */ |
| 114 | int ddr_refresh_rate_config; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 115 | } __packed; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 116 | |
| 117 | #endif |